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dpavlin |
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#ifndef CPU_ALPHA_H |
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#define CPU_ALPHA_H |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_alpha.h,v 1.25 2005/10/22 17:24:22 debug Exp $ |
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dpavlin |
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*/ |
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#include "misc.h" |
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struct cpu_family; |
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#define ALPHA_V0 0 |
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#define ALPHA_A0 16 |
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#define ALPHA_A1 17 |
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#define ALPHA_A2 18 |
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#define ALPHA_A3 19 |
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#define ALPHA_A4 20 |
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#define ALPHA_A5 21 |
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#define ALPHA_RA 26 |
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#define ALPHA_T12 27 |
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#define ALPHA_SP 30 |
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#define ALPHA_ZERO 31 |
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#define N_ALPHA_REGS 32 |
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#define ALPHA_REG_NAMES { \ |
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"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \ |
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"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \ |
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"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \ |
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"t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" } |
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#define ALPHA_N_IC_ARGS 3 |
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#define ALPHA_INSTR_ALIGNMENT_SHIFT 2 |
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#define ALPHA_IC_ENTRIES_SHIFT 11 |
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#define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT) |
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#define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \ |
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& (ALPHA_IC_ENTRIES_PER_PAGE-1)) |
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#define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \ |
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+ ALPHA_INSTR_ALIGNMENT_SHIFT)) |
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struct alpha_instr_call { |
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void (*f)(struct cpu *, struct alpha_instr_call *); |
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size_t arg[ALPHA_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct alpha_tc_physpage { |
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dpavlin |
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struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1]; |
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dpavlin |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint32_t physaddr; |
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int flags; |
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}; |
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/* |
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* Virtual->physical->host page entry: |
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* |
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* 13 + 13 + 13 bits = 39 bits (should be enough for most userspace |
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* applications) |
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* |
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* There is also an additional check for kernel space addresses. |
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*/ |
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#define ALPHA_TOPSHIFT 39 |
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#define ALPHA_TOP_KERNEL 0x1fffff8 |
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#define ALPHA_LEVEL0_SHIFT 26 |
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#define ALPHA_LEVEL0 8192 |
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#define ALPHA_LEVEL1_SHIFT 13 |
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#define ALPHA_LEVEL1 8192 |
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struct alpha_vph_page { |
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void *host_load[ALPHA_LEVEL1]; |
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void *host_store[ALPHA_LEVEL1]; |
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uint64_t phys_addr[ALPHA_LEVEL1]; |
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struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1]; |
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int refcount; |
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struct alpha_vph_page *next; /* Freelist, used if refcount = 0. */ |
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}; |
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#define ALPHA_MAX_VPH_TLB_ENTRIES 128 |
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struct alpha_vpg_tlb_entry { |
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int valid; |
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int writeflag; |
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int64_t timestamp; |
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unsigned char *host_page; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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struct alpha_cpu { |
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/* |
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* General Purpose Registers: |
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*/ |
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uint64_t r[N_ALPHA_REGS]; /* Integer */ |
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uint64_t f[N_ALPHA_REGS]; /* Floating Point */ |
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/* Misc.: */ |
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uint64_t pcc; /* Cycle Counter */ |
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uint64_t ipl; |
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uint64_t load_linked_addr; |
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int ll_flag; |
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/* |
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* Instruction translation cache: |
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*/ |
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/* cur_ic_page is a pointer to an array of ALPHA_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct alpha_tc_physpage *cur_physpage; |
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struct alpha_instr_call *cur_ic_page; |
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struct alpha_instr_call *next_ic; |
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/* |
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* Virtual -> physical -> host address translation: |
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*/ |
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struct alpha_vpg_tlb_entry vph_tlb_entry[ALPHA_MAX_VPH_TLB_ENTRIES]; |
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struct alpha_vph_page *vph_default_page; |
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struct alpha_vph_page *vph_next_free_page; |
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struct alpha_vph_table *vph_next_free_table; |
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struct alpha_vph_page *vph_table0[ALPHA_LEVEL0]; |
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struct alpha_vph_page *vph_table0_kernel[ALPHA_LEVEL0]; |
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}; |
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/* cpu_alpha.c: */ |
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void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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dpavlin |
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void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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dpavlin |
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void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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dpavlin |
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int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem, |
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uint64_t vaddr, unsigned char *data, size_t len, int writeflag, |
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int cache_flags); |
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int alpha_cpu_family_init(struct cpu_family *); |
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/* cpu_alpha_palcode.c: */ |
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void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen); |
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void alpha_palcode(struct cpu *cpu, uint32_t palcode); |
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#endif /* CPU_ALPHA_H */ |