28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu.h,v 1.62 2006/02/09 22:40:27 debug Exp $ |
* $Id: cpu.h,v 1.75 2006/06/16 18:31:26 debug Exp $ |
32 |
* |
* |
33 |
* CPU-related definitions. |
* CPU-related definitions. |
34 |
*/ |
*/ |
43 |
|
|
44 |
/* |
/* |
45 |
* Dyntrans misc declarations, used throughout the dyntrans code. |
* Dyntrans misc declarations, used throughout the dyntrans code. |
46 |
|
* |
47 |
|
* Note that there is place for all instruction calls within a page, |
48 |
|
* and then 2 more. The first one of these "extra" instruction slots is |
49 |
|
* the end-of-page slot. It transfers control to the first instruction |
50 |
|
* slot on the next (virtual) page. |
51 |
|
* |
52 |
|
* The second of these extra instruction slots is an additional |
53 |
|
* end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch |
54 |
|
* instruction can "nullify" (skip) the delay-slot. If the end-of-page |
55 |
|
* slot is skipped, then we end up one step after that. That's where the |
56 |
|
* end_of_page2 slot is. :) |
57 |
*/ |
*/ |
58 |
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
59 |
arch ## _instr_call { \ |
arch ## _instr_call { \ |
63 |
\ |
\ |
64 |
/* Translation cache struct for each physical page: */ \ |
/* Translation cache struct for each physical page: */ \ |
65 |
struct arch ## _tc_physpage { \ |
struct arch ## _tc_physpage { \ |
66 |
struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+1];\ |
struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
67 |
uint32_t next_ofs; /* (0 for end of chain) */ \ |
uint32_t next_ofs; /* (0 for end of chain) */ \ |
68 |
int flags; \ |
int flags; \ |
69 |
addrtype physaddr; \ |
addrtype physaddr; \ |
78 |
int64_t timestamp; \ |
int64_t timestamp; \ |
79 |
}; |
}; |
80 |
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|
81 |
|
#define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \ |
82 |
|
struct arch ## _l3_64_table { \ |
83 |
|
unsigned char *host_load[1 << ARCH ## _L3N]; \ |
84 |
|
unsigned char *host_store[1 << ARCH ## _L3N]; \ |
85 |
|
uint64_t phys_addr[1 << ARCH ## _L3N]; \ |
86 |
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tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \ |
87 |
|
struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \ |
88 |
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struct arch ## _l3_64_table *next; \ |
89 |
|
int refcount; \ |
90 |
|
}; \ |
91 |
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struct arch ## _l2_64_table { \ |
92 |
|
struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \ |
93 |
|
struct arch ## _l2_64_table *next; \ |
94 |
|
int refcount; \ |
95 |
|
}; |
96 |
|
|
97 |
/* |
/* |
98 |
* Dyntrans "Instruction Translation Cache": |
* Dyntrans "Instruction Translation Cache": |
99 |
* |
* |
171 |
* Usage: e.g. VPH64(alpha,ALPHA,uint8_t) |
* Usage: e.g. VPH64(alpha,ALPHA,uint8_t) |
172 |
* or VPH64(sparc,SPARC,uint16_t) |
* or VPH64(sparc,SPARC,uint16_t) |
173 |
* |
* |
174 |
* TODO |
* l1_64 is an array containing poiners to l2 tables. |
175 |
|
* |
176 |
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* l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL |
177 |
|
* pointers in l1_64 for unused slots, a pointer to the dummy table can be |
178 |
|
* used. |
179 |
*/ |
*/ |
180 |
#define VPH64(arch,ARCH,tlbindextype) \ |
#define DYNTRANS_L1N 17 |
181 |
int dummy; |
#define VPH64(arch,ARCH,tlbindextype) \ |
182 |
|
struct arch ## _l3_64_table *l3_64_dummy; \ |
183 |
|
struct arch ## _l3_64_table *next_free_l3; \ |
184 |
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struct arch ## _l2_64_table *l2_64_dummy; \ |
185 |
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struct arch ## _l2_64_table *next_free_l2; \ |
186 |
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struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N]; |
187 |
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188 |
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189 |
|
/* Include all CPUs' header files here: */ |
190 |
#include "cpu_alpha.h" |
#include "cpu_alpha.h" |
191 |
#include "cpu_arm.h" |
#include "cpu_arm.h" |
192 |
#include "cpu_avr.h" |
#include "cpu_avr.h" |
221 |
uint64_t *valuep, int *match_register); |
uint64_t *valuep, int *match_register); |
222 |
int (*disassemble_instr)(struct cpu *cpu, |
int (*disassemble_instr)(struct cpu *cpu, |
223 |
unsigned char *instr, int running, |
unsigned char *instr, int running, |
224 |
uint64_t dumpaddr, int bintrans); |
uint64_t dumpaddr); |
225 |
void (*register_dump)(struct cpu *cpu, |
void (*register_dump)(struct cpu *cpu, |
226 |
int gprs, int coprocs); |
int gprs, int coprocs); |
227 |
int (*run)(struct emul *emul, |
int (*run)(struct emul *emul, |
228 |
struct machine *machine); |
struct machine *machine); |
229 |
void (*dumpinfo)(struct cpu *cpu); |
void (*dumpinfo)(struct cpu *cpu); |
|
void (*show_full_statistics)(struct machine *m); |
|
230 |
void (*tlbdump)(struct machine *m, int x, |
void (*tlbdump)(struct machine *m, int x, |
231 |
int rawflag); |
int rawflag); |
232 |
int (*interrupt)(struct cpu *cpu, uint64_t irq_nr); |
int (*interrupt)(struct cpu *cpu, uint64_t irq_nr); |
234 |
uint64_t irq_nr); |
uint64_t irq_nr); |
235 |
void (*functioncall_trace)(struct cpu *, |
void (*functioncall_trace)(struct cpu *, |
236 |
uint64_t f, int n_args); |
uint64_t f, int n_args); |
237 |
|
char *(*gdb_stub)(struct cpu *, char *cmd); |
238 |
}; |
}; |
239 |
|
|
240 |
|
|
249 |
#define TRANSLATIONS 1 |
#define TRANSLATIONS 1 |
250 |
#define COMBINATIONS 2 |
#define COMBINATIONS 2 |
251 |
|
|
252 |
|
/* Meaning of delay_slot: */ |
253 |
|
#define NOT_DELAYED 0 |
254 |
|
#define DELAYED 1 |
255 |
|
#define TO_BE_DELAYED 2 |
256 |
|
#define EXCEPTION_IN_DELAY_SLOT 0x100 |
257 |
|
|
258 |
|
#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
259 |
|
#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
260 |
|
|
261 |
#define DYNTRANS_CACHE_SIZE (16*1048576) |
#define DYNTRANS_CACHE_SIZE (16*1048576) |
262 |
#define DYNTRANS_CACHE_MARGIN 300000 |
#define DYNTRANS_CACHE_MARGIN 300000 |
263 |
|
|
265 |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
266 |
|
|
267 |
|
|
|
#ifdef DYNTRANS_BACKEND |
|
|
|
|
|
/* TODO: convert this into a fixed-size array? Might increase performace. */ |
|
|
struct dtb_fixup { |
|
|
struct dtb_fixup *next; |
|
|
int type; /* Fixup type [optional] */ |
|
|
void *addr; /* Address of the instruction |
|
|
(in host memory) */ |
|
|
size_t data; /* Emulation data. */ |
|
|
}; |
|
|
|
|
|
struct translation_context { |
|
|
/* Current address of where to emit host instructions: */ |
|
|
/* (NULL means no translation is currently being done.) */ |
|
|
void *p; |
|
|
|
|
|
/* index of the instr_call of the first translated instruction: */ |
|
|
void *ic_page; |
|
|
int start_instr_call_index; |
|
|
|
|
|
/* Fixups needed after first translation pass: */ |
|
|
struct dtb_fixup *fixups; |
|
|
|
|
|
int n_simple; |
|
|
|
|
|
/* translation_buffer should have room for max_size bytes, |
|
|
plus some margin. */ |
|
|
unsigned char *translation_buffer; |
|
|
size_t cur_size; |
|
|
}; |
|
|
|
|
|
#define DTB_TRANSLATION_SIZE_MAX 3072 |
|
|
#define DTB_TRANSLATION_SIZE_MARGIN 1024 |
|
|
|
|
|
void cpu_dtb_add_fixup(struct cpu *cpu, int type, void *addr, size_t data); |
|
|
void cpu_dtb_do_fixups(struct cpu *cpu); |
|
|
|
|
|
void dtb_host_cacheinvalidate(void *p, size_t len); |
|
|
int dtb_function_prologue(struct translation_context *ctx, size_t *sizep); |
|
|
int dtb_function_epilogue(struct translation_context *ctx, size_t *sizep); |
|
|
int dtb_generate_fcall(struct cpu *cpu, struct translation_context *ctx, |
|
|
size_t *sizep, size_t f, size_t instr_call_ptr); |
|
|
int dtb_generate_ptr_inc(struct cpu *cpu, struct translation_context *ctx, |
|
|
size_t *sizep, void *ptr, int amount); |
|
|
|
|
|
#endif /* DYNTRANS_BACKEND */ |
|
|
|
|
|
|
|
|
|
|
268 |
/* |
/* |
269 |
* The generic CPU struct: |
* The generic CPU struct: |
270 |
*/ |
*/ |
296 |
void (*invalidate_code_translation)(struct cpu *, |
void (*invalidate_code_translation)(struct cpu *, |
297 |
uint64_t paddr, int flags); |
uint64_t paddr, int flags); |
298 |
void (*useremul_syscall)(struct cpu *cpu, uint32_t code); |
void (*useremul_syscall)(struct cpu *cpu, uint32_t code); |
299 |
|
int (*instruction_has_delayslot)(struct cpu *cpu, |
300 |
|
unsigned char *ib); |
301 |
|
|
302 |
uint64_t pc; |
uint64_t pc; |
303 |
|
|
|
#ifdef TRACE_NULL_CRASHES |
|
|
/* TODO: remove this, it's MIPS only */ |
|
|
int trace_null_index; |
|
|
uint64_t trace_null_addr[TRACE_NULL_N_ENTRIES]; |
|
|
#endif |
|
|
|
|
304 |
int trace_tree_depth; |
int trace_tree_depth; |
305 |
|
|
306 |
/* |
/* |
310 |
int n_translated_instrs; |
int n_translated_instrs; |
311 |
unsigned char *translation_cache; |
unsigned char *translation_cache; |
312 |
size_t translation_cache_cur_ofs; |
size_t translation_cache_cur_ofs; |
313 |
#ifdef DYNTRANS_BACKEND |
|
314 |
struct translation_context translation_context; |
uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ |
315 |
#endif |
int delay_slot; |
316 |
|
|
317 |
/* |
/* |
318 |
* CPU-family dependent: |
* CPU-family dependent: |
337 |
/* cpu.c: */ |
/* cpu.c: */ |
338 |
struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
339 |
int cpu_id, char *cpu_type_name); |
int cpu_id, char *cpu_type_name); |
|
void cpu_show_full_statistics(struct machine *m); |
|
340 |
void cpu_tlbdump(struct machine *m, int x, int rawflag); |
void cpu_tlbdump(struct machine *m, int x, int rawflag); |
341 |
void cpu_register_match(struct machine *m, char *name, |
void cpu_register_match(struct machine *m, char *name, |
342 |
int writeflag, uint64_t *valuep, int *match_register); |
int writeflag, uint64_t *valuep, int *match_register); |
343 |
void cpu_register_dump(struct machine *m, struct cpu *cpu, |
void cpu_register_dump(struct machine *m, struct cpu *cpu, |
344 |
int gprs, int coprocs); |
int gprs, int coprocs); |
345 |
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
346 |
unsigned char *instr, int running, uint64_t addr, int bintrans); |
unsigned char *instr, int running, uint64_t addr); |
347 |
|
char *cpu_gdb_stub(struct cpu *cpu, char *cmd); |
348 |
int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
349 |
int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
350 |
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
383 |
fp->interrupt = n ## _cpu_interrupt; \ |
fp->interrupt = n ## _cpu_interrupt; \ |
384 |
fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
385 |
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
386 |
return 1; \ |
fp->gdb_stub = n ## _cpu_gdb_stub; \ |
|
} |
|
|
|
|
|
#define CPU_OLD_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
|
|
struct cpu_family *fp) { \ |
|
|
/* Fill in the cpu_family struct with valid data for this arch. */ \ |
|
|
fp->name = s; \ |
|
|
fp->cpu_new = n ## _cpu_new; \ |
|
|
fp->list_available_types = n ## _cpu_list_available_types; \ |
|
|
fp->register_match = n ## _cpu_register_match; \ |
|
|
fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
|
|
fp->register_dump = n ## _cpu_register_dump; \ |
|
|
fp->run = n ## _OLD_cpu_run; \ |
|
|
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
|
|
fp->show_full_statistics = n ## _cpu_show_full_statistics; \ |
|
387 |
fp->tlbdump = n ## _cpu_tlbdump; \ |
fp->tlbdump = n ## _cpu_tlbdump; \ |
|
fp->interrupt = n ## _cpu_interrupt; \ |
|
|
fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
|
|
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
|
388 |
return 1; \ |
return 1; \ |
389 |
} |
} |
390 |
|
|