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#define CPU_H |
#define CPU_H |
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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu.h,v 1.48 2005/09/17 17:14:28 debug Exp $ |
* $Id: cpu.h,v 1.62 2006/02/09 22:40:27 debug Exp $ |
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* |
* |
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* See cpu.c. |
* CPU-related definitions. |
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*/ |
*/ |
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#include <inttypes.h> |
#include <inttypes.h> |
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#include <sys/time.h> |
#include <sys/time.h> |
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/* This is needed for undefining 'mips' or 'ppc', on weird systems: */ |
/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ |
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#include "../../config.h" |
#include "../../config.h" |
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/* |
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* Dyntrans misc declarations, used throughout the dyntrans code. |
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*/ |
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#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
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arch ## _instr_call { \ |
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void (*f)(struct cpu *, struct arch ## _instr_call *); \ |
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size_t arg[ARCH ## _N_IC_ARGS]; \ |
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}; \ |
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\ |
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/* Translation cache struct for each physical page: */ \ |
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struct arch ## _tc_physpage { \ |
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struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+1];\ |
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uint32_t next_ofs; /* (0 for end of chain) */ \ |
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int flags; \ |
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addrtype physaddr; \ |
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}; \ |
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\ |
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struct arch ## _vpg_tlb_entry { \ |
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uint8_t valid; \ |
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uint8_t writeflag; \ |
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addrtype vaddr_page; \ |
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addrtype paddr_page; \ |
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unsigned char *host_page; \ |
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int64_t timestamp; \ |
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}; |
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/* |
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* Dyntrans "Instruction Translation Cache": |
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* |
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* cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to |
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* be the same as cur_ic_page, because all the instrcalls should be placed |
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* first in the physpage struct!) |
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* |
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* cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE |
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* instruction call entries. |
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* |
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* next_ic points to the next such instruction call to be executed. |
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* |
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* combination_check, when set to non-NULL, is executed automatically after |
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* an instruction has been translated. (It check for combinations of |
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* instructions; low_addr is the offset of the translated instruction in the |
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* current page, NOT shifted right.) |
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*/ |
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#define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \ |
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struct arch ## _instr_call *cur_ic_page; \ |
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struct arch ## _instr_call *next_ic; \ |
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void (*combination_check)(struct cpu *, \ |
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struct arch ## _instr_call *, int low_addr); |
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/* |
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* Virtual -> physical -> host address translation TLB entries: |
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* ------------------------------------------------------------ |
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* |
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* Regardless of whether 32-bit or 64-bit address translation is used, the |
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* same TLB entry structure is used. |
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*/ |
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#define VPH_TLBS(arch,ARCH) \ |
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struct arch ## _vpg_tlb_entry \ |
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vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES]; |
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/* |
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* 32-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* This stuff assumes that 4 KB pages are used. 20 bits to select a page |
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* means just 1 M entries needed. This is small enough that a couple of |
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* full-size tables can fit in virtual memory on modern hosts (both 32-bit |
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* and 64-bit hosts). :-) |
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* |
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* Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t) |
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* or VPH32(sparc,SPARC,uint64_t,uint16_t) |
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* |
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* The vph_tlb_entry entries are cpu dependent tlb entries. |
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* |
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* The host_load and host_store entries point to host pages; the phys_addr |
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* entries are uint32_t or uint64_t (emulated physical addresses). |
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* |
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* phys_page points to translation cache physpages. |
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* |
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* phystranslation is a bitmap which tells us whether a physical page has |
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* a code translation. |
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* |
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* vaddr_to_tlbindex is a virtual address to tlb index hint table. |
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* The values in this array are the tlb index plus 1, so a value of, say, |
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* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which |
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* is not a valid index. (I.e. no hit.) |
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*/ |
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#define N_VPH32_ENTRIES 1048576 |
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#define VPH32(arch,ARCH,paddrtype,tlbindextype) \ |
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unsigned char *host_load[N_VPH32_ENTRIES]; \ |
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unsigned char *host_store[N_VPH32_ENTRIES]; \ |
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paddrtype phys_addr[N_VPH32_ENTRIES]; \ |
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struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
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uint32_t phystranslation[N_VPH32_ENTRIES/32]; \ |
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tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
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/* |
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* 64-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* Usage: e.g. VPH64(alpha,ALPHA,uint8_t) |
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* or VPH64(sparc,SPARC,uint16_t) |
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* |
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* TODO |
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*/ |
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#define VPH64(arch,ARCH,tlbindextype) \ |
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int dummy; |
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#include "cpu_alpha.h" |
#include "cpu_alpha.h" |
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#include "cpu_arm.h" |
#include "cpu_arm.h" |
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#include "cpu_avr.h" |
#include "cpu_avr.h" |
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uint64_t f, int n_args); |
uint64_t f, int n_args); |
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}; |
}; |
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#ifdef TRACE_NULL_CRASHES |
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#define TRACE_NULL_N_ENTRIES 16 |
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#endif |
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/* |
/* |
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* Dynamic translation definitions: |
* More dyntrans stuff: |
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* |
* |
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* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
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* into the cache, for possible translation cache structs for physical pages. |
* into the cache, for possible translation cache structs for physical pages. |
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#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
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#ifdef DYNTRANS_BACKEND |
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/* TODO: convert this into a fixed-size array? Might increase performace. */ |
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struct dtb_fixup { |
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struct dtb_fixup *next; |
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int type; /* Fixup type [optional] */ |
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void *addr; /* Address of the instruction |
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(in host memory) */ |
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size_t data; /* Emulation data. */ |
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}; |
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struct translation_context { |
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/* Current address of where to emit host instructions: */ |
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/* (NULL means no translation is currently being done.) */ |
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void *p; |
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/* index of the instr_call of the first translated instruction: */ |
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void *ic_page; |
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int start_instr_call_index; |
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/* Fixups needed after first translation pass: */ |
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struct dtb_fixup *fixups; |
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int n_simple; |
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/* translation_buffer should have room for max_size bytes, |
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plus some margin. */ |
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unsigned char *translation_buffer; |
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size_t cur_size; |
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}; |
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#define DTB_TRANSLATION_SIZE_MAX 3072 |
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#define DTB_TRANSLATION_SIZE_MARGIN 1024 |
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void cpu_dtb_add_fixup(struct cpu *cpu, int type, void *addr, size_t data); |
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void cpu_dtb_do_fixups(struct cpu *cpu); |
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void dtb_host_cacheinvalidate(void *p, size_t len); |
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int dtb_function_prologue(struct translation_context *ctx, size_t *sizep); |
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int dtb_function_epilogue(struct translation_context *ctx, size_t *sizep); |
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int dtb_generate_fcall(struct cpu *cpu, struct translation_context *ctx, |
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size_t *sizep, size_t f, size_t instr_call_ptr); |
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int dtb_generate_ptr_inc(struct cpu *cpu, struct translation_context *ctx, |
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size_t *sizep, void *ptr, int amount); |
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#endif /* DYNTRANS_BACKEND */ |
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/* |
/* |
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* The generic CPU struct: |
* The generic CPU struct: |
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*/ |
*/ |
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void (*update_translation_table)(struct cpu *, |
void (*update_translation_table)(struct cpu *, |
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uint64_t vaddr_page, unsigned char *host_page, |
uint64_t vaddr_page, unsigned char *host_page, |
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int writeflag, uint64_t paddr_page); |
int writeflag, uint64_t paddr_page); |
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void (*invalidate_translation_caches_paddr)(struct cpu *, |
void (*invalidate_translation_caches)(struct cpu *, |
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uint64_t paddr, int flags); |
uint64_t paddr, int flags); |
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void (*invalidate_code_translation)(struct cpu *, |
void (*invalidate_code_translation)(struct cpu *, |
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uint64_t paddr, int flags); |
uint64_t paddr, int flags); |
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int n_translated_instrs; |
int n_translated_instrs; |
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unsigned char *translation_cache; |
unsigned char *translation_cache; |
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size_t translation_cache_cur_ofs; |
size_t translation_cache_cur_ofs; |
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#ifdef DYNTRANS_BACKEND |
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struct translation_context translation_context; |
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#endif |
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/* |
/* |
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* CPU-family dependent: |
* CPU-family dependent: |
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#define INVALIDATE_ALL 2 |
#define INVALIDATE_ALL 2 |
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#define INVALIDATE_PADDR 4 |
#define INVALIDATE_PADDR 4 |
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#define INVALIDATE_VADDR 8 |
#define INVALIDATE_VADDR 8 |
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#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ |
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#define TLB_CODE 0x02 |
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#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
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fp->register_dump = n ## _cpu_register_dump; \ |
fp->register_dump = n ## _cpu_register_dump; \ |
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fp->run = n ## _cpu_run; \ |
fp->run = n ## _cpu_run; \ |
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fp->dumpinfo = n ## _cpu_dumpinfo; \ |
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
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fp->interrupt = n ## _cpu_interrupt; \ |
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fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
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fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
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return 1; \ |
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} |
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#define CPU_OLD_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
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struct cpu_family *fp) { \ |
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/* Fill in the cpu_family struct with valid data for this arch. */ \ |
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fp->name = s; \ |
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fp->cpu_new = n ## _cpu_new; \ |
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fp->list_available_types = n ## _cpu_list_available_types; \ |
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fp->register_match = n ## _cpu_register_match; \ |
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fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
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fp->register_dump = n ## _cpu_register_dump; \ |
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fp->run = n ## _OLD_cpu_run; \ |
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fp->dumpinfo = n ## _cpu_dumpinfo; \ |
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fp->show_full_statistics = n ## _cpu_show_full_statistics; \ |
fp->show_full_statistics = n ## _cpu_show_full_statistics; \ |
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fp->tlbdump = n ## _cpu_tlbdump; \ |
fp->tlbdump = n ## _cpu_tlbdump; \ |
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fp->interrupt = n ## _cpu_interrupt; \ |
fp->interrupt = n ## _cpu_interrupt; \ |