src/include/bus_pci.h

#ifndef BUS_PCI_H
#define BUS_PCI_H

/*
 *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: bus_pci.h,v 1.30 2006/08/12 19:32:20 debug Exp $
 */

#include "misc.h"
#include "pcireg.h"

struct machine;
struct memory;

struct pci_device;


#ifndef BUS_PCI_C

struct pci_data;

#else

struct pci_data {
        /*  IRQ nr of the controller itself.  */
        int             irq_nr;

        /*
         *  Default I/O port, memory, and irq bases for PCI and legacy ISA
         *  devices, and the base address for actual (emulated) devices:
         *
         *  pci_portbase etc are what is stored in the device configuration
         *  registers. This address + pci_actual_{io,mem}_offset is where the
         *  emulated device should be registered.
         */
        uint64_t        pci_actual_io_offset;
        uint64_t        pci_actual_mem_offset;

        uint64_t        pci_portbase;
        uint64_t        pci_membase;
        int             pci_irqbase;

        uint64_t        isa_portbase;
        uint64_t        isa_membase;
        int             isa_irqbase;

        /*  Current base when allocating space for PCI devices:  */
        uint64_t        cur_pci_portbase;
        uint64_t        cur_pci_membase;

        /*  Current register access:  */
        int             cur_bus, cur_device, cur_func, cur_reg;
        int             last_was_write_ffffffff;

        struct pci_device *first_device;
};

#define PCI_CFG_MEM_SIZE        0x100

struct pci_device {
        /*  Pointer to the next PCI device on this bus:  */
        struct pci_device       *next;

        /*  Pointer back to the bus this device is connected to:  */
        struct pci_data         *pcibus;

        /*  Short device name, and bus/device/function value:  */
        char                    *name;
        int                     bus, device, function;

        /*  Configuration memory:  */
        unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
        unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];

        /*  Used when setting up the configuration registers:  */
        int                     cur_mapreg_offset;

        /*  Function to handle device-specific cfg register writes:  */
        int                     (*cfg_reg_write)(struct pci_device *pd,
                                    int reg, uint32_t value);
        void                    *extra;
};

#define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
        struct memory *mem, struct pci_device *pd)

/*
 *  Store little-endian config data in the pci_data struct's cfg_mem[]
 *  or cfg_mem_size[], respectively.
 */
#define PCI_SET_DATA(ofs,value) {                                       \
        pd->cfg_mem[(ofs)]     = (value) & 255;                         \
        pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255;                  \
        pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255;                 \
        pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255;                 \
        }
#define PCI_SET_DATA_SIZE(ofs,value)    {                               \
        pd->cfg_mem_size[(ofs)]     = (value) & 255;                    \
        pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255;             \
        pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255;            \
        pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255;            \
        }

#endif

#define BUS_PCI_ADDR    0xcf8
#define BUS_PCI_DATA    0xcfc


/*
 *  bus_pci.c:
 */

/*  Run-time access:  */
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg);
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
        int bus, int device, int function, int reg);
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
        uint64_t *data, int len, int writeflag);

/*  Initialization:  */
struct pci_data *bus_pci_init(struct machine *machine, int irq_nr,
        uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
        uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,
        uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);

/*  Add a PCI device to a PCI bus:  */
void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
        struct memory *mem, int bus, int device, int function,
        const char *name);


#endif  /*  BUS_PCI_H  */
1	dpavlin	20	#ifndef BUS_PCI_H
2			#define BUS_PCI_H
3	dpavlin	4
4			/*
5	dpavlin	22	* Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
6	dpavlin	4	*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	30	* $Id: bus_pci.h,v 1.30 2006/08/12 19:32:20 debug Exp $
32	dpavlin	4	*/
33
34			#include "misc.h"
35	dpavlin	20	#include "pcireg.h"
36	dpavlin	4
37			struct machine;
38			struct memory;
39
40	dpavlin	20	struct pci_device;
41	dpavlin	4
42	dpavlin	30
43	dpavlin	20	#ifndef BUS_PCI_C
44	dpavlin	30
45	dpavlin	20	struct pci_data;
46	dpavlin	30
47	dpavlin	20	#else
48	dpavlin	4
49			struct pci_data {
50	dpavlin	20	/* IRQ nr of the controller itself. */
51	dpavlin	4	int irq_nr;
52	dpavlin	20
53			/*
54			* Default I/O port, memory, and irq bases for PCI and legacy ISA
55			* devices, and the base address for actual (emulated) devices:
56			*
57			* pci_portbase etc are what is stored in the device configuration
58			* registers. This address + pci_actual_{io,mem}_offset is where the
59			* emulated device should be registered.
60			*/
61			uint64_t pci_actual_io_offset;
62			uint64_t pci_actual_mem_offset;
63
64			uint64_t pci_portbase;
65			uint64_t pci_membase;
66			int pci_irqbase;
67
68			uint64_t isa_portbase;
69			uint64_t isa_membase;
70			int isa_irqbase;
71
72			/* Current base when allocating space for PCI devices: */
73			uint64_t cur_pci_portbase;
74			uint64_t cur_pci_membase;
75
76	dpavlin	22	/* Current register access: */
77			int cur_bus, cur_device, cur_func, cur_reg;
78	dpavlin	4	int last_was_write_ffffffff;
79
80			struct pci_device *first_device;
81			};
82
83	dpavlin	20	#define PCI_CFG_MEM_SIZE 0x100
84	dpavlin	4
85	dpavlin	20	struct pci_device {
86	dpavlin	30	/* Pointer to the next PCI device on this bus: */
87	dpavlin	20	struct pci_device *next;
88	dpavlin	30
89			/* Pointer back to the bus this device is connected to: */
90	dpavlin	20	struct pci_data *pcibus;
91	dpavlin	30
92			/* Short device name, and bus/device/function value: */
93	dpavlin	20	char *name;
94			int bus, device, function;
95	dpavlin	30
96			/* Configuration memory: */
97	dpavlin	20	unsigned char cfg_mem[PCI_CFG_MEM_SIZE];
98			unsigned char cfg_mem_size[PCI_CFG_MEM_SIZE];
99	dpavlin	30
100			/* Used when setting up the configuration registers: */
101	dpavlin	22	int cur_mapreg_offset;
102	dpavlin	30
103			/* Function to handle device-specific cfg register writes: */
104			int (cfg_reg_write)(struct pci_device pd,
105			int reg, uint32_t value);
106			void *extra;
107	dpavlin	20	};
108	dpavlin	4
109	dpavlin	20	#define PCIINIT(name) void pciinit_ ## name(struct machine *machine, \
110			struct memory mem, struct pci_device pd)
111	dpavlin	4
112			/*
113	dpavlin	20	* Store little-endian config data in the pci_data struct's cfg_mem[]
114			* or cfg_mem_size[], respectively.
115	dpavlin	4	*/
116	dpavlin	20	#define PCI_SET_DATA(ofs,value) { \
117			pd->cfg_mem[(ofs)] = (value) & 255; \
118			pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255; \
119			pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255; \
120			pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255; \
121			}
122			#define PCI_SET_DATA_SIZE(ofs,value) { \
123			pd->cfg_mem_size[(ofs)] = (value) & 255; \
124			pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255; \
125			pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255; \
126			pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255; \
127			}
128	dpavlin	4
129	dpavlin	20	#endif
130	dpavlin	14
131	dpavlin	20	#define BUS_PCI_ADDR 0xcf8
132			#define BUS_PCI_DATA 0xcfc
133	dpavlin	4
134
135	dpavlin	22	/*
136			* bus_pci.c:
137			*/
138
139			/* Run-time access: */
140			void bus_pci_decompose_1(uint32_t t, int bus, int dev, int func, int reg);
141			void bus_pci_setaddr(struct cpu cpu, struct pci_data pci_data,
142			int bus, int device, int function, int reg);
143			void bus_pci_data_access(struct cpu cpu, struct pci_data pci_data,
144			uint64_t *data, int len, int writeflag);
145
146			/* Initialization: */
147			struct pci_data bus_pci_init(struct machine machine, int irq_nr,
148	dpavlin	20	uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
149			uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,
150			uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);
151	dpavlin	30
152			/* Add a PCI device to a PCI bus: */
153	dpavlin	22	void bus_pci_add(struct machine machine, struct pci_data pci_data,
154			struct memory *mem, int bus, int device, int function,
155			const char *name);
156	dpavlin	4
157	dpavlin	14
158	dpavlin	20	#endif /* BUS_PCI_H */