25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_sh4.c,v 1.39 2007/04/13 16:12:39 debug Exp $ |
* $Id: dev_sh4.c,v 1.48 2007/05/01 04:03:09 debug Exp $ |
29 |
* |
* |
30 |
* SH4 processor specific memory mapped registers (0xf0000000 - 0xffffffff). |
* SH4 processor specific memory mapped registers (0xf0000000 - 0xffffffff). |
31 |
* |
* |
42 |
#include <stdlib.h> |
#include <stdlib.h> |
43 |
#include <string.h> |
#include <string.h> |
44 |
|
|
45 |
|
#include "bus_pci.h" |
46 |
#include "console.h" |
#include "console.h" |
47 |
#include "cpu.h" |
#include "cpu.h" |
48 |
#include "device.h" |
#include "device.h" |
59 |
#include "sh4_exception.h" |
#include "sh4_exception.h" |
60 |
#include "sh4_intcreg.h" |
#include "sh4_intcreg.h" |
61 |
#include "sh4_mmu.h" |
#include "sh4_mmu.h" |
62 |
|
#include "sh4_pcicreg.h" |
63 |
#include "sh4_rtcreg.h" |
#include "sh4_rtcreg.h" |
64 |
#include "sh4_scifreg.h" |
#include "sh4_scifreg.h" |
65 |
#include "sh4_scireg.h" |
#include "sh4_scireg.h" |
70 |
#define SH4_TICK_SHIFT 14 |
#define SH4_TICK_SHIFT 14 |
71 |
#define N_SH4_TIMERS 3 |
#define N_SH4_TIMERS 3 |
72 |
|
|
73 |
|
/* PCI stuff: */ |
74 |
|
#define N_PCIC_REGS (0x224 / sizeof(uint32_t)) |
75 |
|
#define N_PCIC_IRQS 16 |
76 |
|
#define PCIC_REG(addr) ((addr - SH4_PCIC) / sizeof(uint32_t)) |
77 |
|
#define PCI_VENDOR_HITACHI 0x1054 |
78 |
|
#define PCI_PRODUCT_HITACHI_SH7751 0x3505 |
79 |
|
#define PCI_PRODUCT_HITACHI_SH7751R 0x350e |
80 |
|
|
81 |
#define SCIF_TX_FIFO_SIZE 16 |
#define SCIF_TX_FIFO_SIZE 16 |
82 |
|
#define SCIF_DELAYED_TX_VALUE 2 /* 2 to be safe, 1 = fast but buggy */ |
83 |
|
|
84 |
/* General-purpose I/O stuff: */ |
/* General-purpose I/O stuff: */ |
85 |
#define SH4_PCTRA 0xff80002c |
#define SH4_PCTRA 0xff80002c |
104 |
int scif_delayed_tx; |
int scif_delayed_tx; |
105 |
int scif_console_handle; |
int scif_console_handle; |
106 |
uint8_t scif_tx_fifo[SCIF_TX_FIFO_SIZE + 1]; |
uint8_t scif_tx_fifo[SCIF_TX_FIFO_SIZE + 1]; |
107 |
int scif_tx_fifo_cursize; |
size_t scif_tx_fifo_cursize; |
108 |
struct interrupt scif_tx_irq; |
struct interrupt scif_tx_irq; |
109 |
struct interrupt scif_rx_irq; |
struct interrupt scif_rx_irq; |
110 |
int scif_tx_irq_asserted; |
int scif_tx_irq_asserted; |
126 |
uint32_t pctrb; /* Port Control Register B */ |
uint32_t pctrb; /* Port Control Register B */ |
127 |
uint32_t pdtrb; /* Port Data Register B */ |
uint32_t pdtrb; /* Port Data Register B */ |
128 |
|
|
129 |
|
/* PCIC (PCI controller): */ |
130 |
|
struct pci_data *pci_data; |
131 |
|
struct interrupt cpu_pcic_interrupt[N_PCIC_IRQS]; |
132 |
|
uint32_t pcic_reg[N_PCIC_REGS]; |
133 |
|
|
134 |
/* SCI (serial interface): */ |
/* SCI (serial interface): */ |
135 |
int sci_bits_outputed; |
int sci_bits_outputed; |
136 |
int sci_bits_read; |
int sci_bits_read; |
221 |
} |
} |
222 |
|
|
223 |
|
|
224 |
|
static void sh4_pcic_interrupt_assert(struct interrupt *interrupt) |
225 |
|
{ |
226 |
|
struct sh4_data *d = interrupt->extra; |
227 |
|
INTERRUPT_ASSERT(d->cpu_pcic_interrupt[interrupt->line]); |
228 |
|
} |
229 |
|
static void sh4_pcic_interrupt_deassert(struct interrupt *interrupt) |
230 |
|
{ |
231 |
|
struct sh4_data *d = interrupt->extra; |
232 |
|
INTERRUPT_DEASSERT(d->cpu_pcic_interrupt[interrupt->line]); |
233 |
|
} |
234 |
|
|
235 |
|
|
236 |
static void scif_reassert_interrupts(struct sh4_data *d) |
static void scif_reassert_interrupts(struct sh4_data *d) |
237 |
{ |
{ |
238 |
int old_tx_asserted = d->scif_tx_irq_asserted; |
int old_tx_asserted = d->scif_tx_irq_asserted; |
260 |
DEVICE_TICK(sh4) |
DEVICE_TICK(sh4) |
261 |
{ |
{ |
262 |
struct sh4_data *d = (struct sh4_data *) extra; |
struct sh4_data *d = (struct sh4_data *) extra; |
263 |
int i; |
unsigned int i; |
264 |
|
|
265 |
/* |
/* |
266 |
* Serial controller interrupts: |
* Serial controller interrupts: |
677 |
} |
} |
678 |
|
|
679 |
|
|
680 |
|
DEVICE_ACCESS(sh4_pcic) |
681 |
|
{ |
682 |
|
struct sh4_data *d = (struct sh4_data *) extra; |
683 |
|
uint64_t idata = 0, odata = 0; |
684 |
|
|
685 |
|
if (writeflag == MEM_WRITE) |
686 |
|
idata = memory_readmax64(cpu, data, len); |
687 |
|
|
688 |
|
relative_addr += SH4_PCIC; |
689 |
|
|
690 |
|
/* Register read/write: */ |
691 |
|
if (writeflag == MEM_WRITE) |
692 |
|
d->pcic_reg[PCIC_REG(relative_addr)] = idata; |
693 |
|
else |
694 |
|
odata = d->pcic_reg[PCIC_REG(relative_addr)]; |
695 |
|
|
696 |
|
/* Special cases: */ |
697 |
|
|
698 |
|
switch (relative_addr) { |
699 |
|
|
700 |
|
case SH4_PCICONF0: |
701 |
|
if (writeflag == MEM_WRITE) { |
702 |
|
fatal("[ sh4_pcic: TODO: Write to SH4_PCICONF0? ]\n"); |
703 |
|
exit(1); |
704 |
|
} else { |
705 |
|
if (strcmp(cpu->cd.sh.cpu_type.name, "SH7751") == 0) { |
706 |
|
odata = PCI_ID_CODE(PCI_VENDOR_HITACHI, |
707 |
|
PCI_PRODUCT_HITACHI_SH7751); |
708 |
|
} else if (strcmp(cpu->cd.sh.cpu_type.name, |
709 |
|
"SH7751R") == 0) { |
710 |
|
odata = PCI_ID_CODE(PCI_VENDOR_HITACHI, |
711 |
|
PCI_PRODUCT_HITACHI_SH7751R); |
712 |
|
} else { |
713 |
|
fatal("sh4_pcic: TODO: PCICONF0 read for" |
714 |
|
" unimplemented CPU type?\n"); |
715 |
|
exit(1); |
716 |
|
} |
717 |
|
} |
718 |
|
break; |
719 |
|
|
720 |
|
case SH4_PCICONF1: |
721 |
|
case SH4_PCICONF2: |
722 |
|
case SH4_PCICR: |
723 |
|
case SH4_PCIBCR1: |
724 |
|
case SH4_PCIBCR2: |
725 |
|
case SH4_PCIBCR3: |
726 |
|
case SH4_PCIWCR1: |
727 |
|
case SH4_PCIWCR2: |
728 |
|
case SH4_PCIWCR3: |
729 |
|
case SH4_PCIMCR: |
730 |
|
break; |
731 |
|
|
732 |
|
case SH4_PCICONF5: |
733 |
|
/* Hardcoded to what OpenBSD/landisk uses: */ |
734 |
|
if (writeflag == MEM_WRITE && idata != 0xac000000) { |
735 |
|
fatal("sh4_pcic: SH4_PCICONF5 unknown value" |
736 |
|
" 0x%"PRIx32"\n", (uint32_t) idata); |
737 |
|
exit(1); |
738 |
|
} |
739 |
|
break; |
740 |
|
|
741 |
|
case SH4_PCICONF6: |
742 |
|
/* Hardcoded to what OpenBSD/landisk uses: */ |
743 |
|
if (writeflag == MEM_WRITE && idata != 0x8c000000) { |
744 |
|
fatal("sh4_pcic: SH4_PCICONF6 unknown value" |
745 |
|
" 0x%"PRIx32"\n", (uint32_t) idata); |
746 |
|
exit(1); |
747 |
|
} |
748 |
|
break; |
749 |
|
|
750 |
|
case SH4_PCILSR0: |
751 |
|
/* Hardcoded to what OpenBSD/landisk uses: */ |
752 |
|
if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) { |
753 |
|
fatal("sh4_pcic: SH4_PCILSR0 unknown value" |
754 |
|
" 0x%"PRIx32"\n", (uint32_t) idata); |
755 |
|
exit(1); |
756 |
|
} |
757 |
|
break; |
758 |
|
|
759 |
|
case SH4_PCILAR0: |
760 |
|
/* Hardcoded to what OpenBSD/landisk uses: */ |
761 |
|
if (writeflag == MEM_WRITE && idata != 0xac000000) { |
762 |
|
fatal("sh4_pcic: SH4_PCILAR0 unknown value" |
763 |
|
" 0x%"PRIx32"\n", (uint32_t) idata); |
764 |
|
exit(1); |
765 |
|
} |
766 |
|
break; |
767 |
|
|
768 |
|
case SH4_PCILSR1: |
769 |
|
/* Hardcoded to what OpenBSD/landisk uses: */ |
770 |
|
if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) { |
771 |
|
fatal("sh4_pcic: SH4_PCILSR1 unknown value" |
772 |
|
" 0x%"PRIx32"\n", (uint32_t) idata); |
773 |
|
exit(1); |
774 |
|
} |
775 |
|
break; |
776 |
|
|
777 |
|
case SH4_PCILAR1: |
778 |
|
/* Hardcoded to what OpenBSD/landisk uses: */ |
779 |
|
if (writeflag == MEM_WRITE && idata != 0xac000000) { |
780 |
|
fatal("sh4_pcic: SH4_PCILAR1 unknown value" |
781 |
|
" 0x%"PRIx32"\n", (uint32_t) idata); |
782 |
|
exit(1); |
783 |
|
} |
784 |
|
break; |
785 |
|
|
786 |
|
case SH4_PCIMBR: |
787 |
|
if (writeflag == MEM_WRITE && idata != SH4_PCIC_MEM) { |
788 |
|
fatal("sh4_pcic: PCIMBR set to 0x%"PRIx32", not" |
789 |
|
" 0x%"PRIx32"? TODO\n", (uint32_t) idata, |
790 |
|
(uint32_t) SH4_PCIC_MEM); |
791 |
|
exit(1); |
792 |
|
} |
793 |
|
break; |
794 |
|
|
795 |
|
case SH4_PCIIOBR: |
796 |
|
if (writeflag == MEM_WRITE && idata != SH4_PCIC_IO) { |
797 |
|
fatal("sh4_pcic: PCIIOBR set to 0x%"PRIx32", not" |
798 |
|
" 0x%"PRIx32"? TODO\n", (uint32_t) idata, |
799 |
|
(uint32_t) SH4_PCIC_IO); |
800 |
|
exit(1); |
801 |
|
} |
802 |
|
break; |
803 |
|
|
804 |
|
case SH4_PCIPAR: |
805 |
|
/* PCI bus access Address Register: */ |
806 |
|
{ |
807 |
|
int bus = (idata >> 16) & 0xff; |
808 |
|
int dev = (idata >> 11) & 0x1f; |
809 |
|
int func = (idata >> 8) & 7; |
810 |
|
int reg = idata & 0xff; |
811 |
|
bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
812 |
|
} |
813 |
|
break; |
814 |
|
|
815 |
|
case SH4_PCIPDR: |
816 |
|
/* PCI bus access Data Register: */ |
817 |
|
bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
818 |
|
&odata : &idata, len, writeflag); |
819 |
|
break; |
820 |
|
|
821 |
|
default:if (writeflag == MEM_READ) { |
822 |
|
fatal("[ sh4_pcic: read from addr 0x%x: TODO ]\n", |
823 |
|
(int)relative_addr); |
824 |
|
} else { |
825 |
|
fatal("[ sh4_pcic: write to addr 0x%x: 0x%x: TODO ]\n", |
826 |
|
(int)relative_addr, (int)idata); |
827 |
|
} |
828 |
|
exit(1); |
829 |
|
} |
830 |
|
|
831 |
|
if (writeflag == MEM_READ) |
832 |
|
memory_writemax64(cpu, data, len, odata); |
833 |
|
|
834 |
|
return 1; |
835 |
|
} |
836 |
|
|
837 |
|
|
838 |
DEVICE_ACCESS(sh4) |
DEVICE_ACCESS(sh4) |
839 |
{ |
{ |
840 |
struct sh4_data *d = (struct sh4_data *) extra; |
struct sh4_data *d = (struct sh4_data *) extra; |
876 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
877 |
odata = cpu->cd.sh.pteh; |
odata = cpu->cd.sh.pteh; |
878 |
else { |
else { |
879 |
int old_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK; |
unsigned int old_asid = cpu->cd.sh.pteh |
880 |
|
& SH4_PTEH_ASID_MASK; |
881 |
cpu->cd.sh.pteh = idata; |
cpu->cd.sh.pteh = idata; |
882 |
|
|
883 |
if ((idata & SH4_PTEH_ASID_MASK) != old_asid) { |
if ((idata & SH4_PTEH_ASID_MASK) != old_asid) { |
938 |
cpu->invalidate_translation_caches(cpu, |
cpu->invalidate_translation_caches(cpu, |
939 |
0, INVALIDATE_ALL); |
0, INVALIDATE_ALL); |
940 |
|
|
941 |
/* Should always read back as 0. */ |
/* The TI bit should always read as 0. */ |
942 |
idata &= ~SH4_MMUCR_TI; |
idata &= ~SH4_MMUCR_TI; |
943 |
} |
} |
944 |
|
|
1316 |
case SHREG_SCSPTR: |
case SHREG_SCSPTR: |
1317 |
odata = sh_sci_access(d, cpu, |
odata = sh_sci_access(d, cpu, |
1318 |
writeflag == MEM_WRITE? 1 : 0, idata); |
writeflag == MEM_WRITE? 1 : 0, idata); |
1319 |
|
|
1320 |
|
/* |
1321 |
|
* TODO |
1322 |
|
* |
1323 |
|
* Find out the REAL way to make OpenBSD/landisk 4.1 run |
1324 |
|
* in a stable manner! This is a SUPER-UGLY HACK which |
1325 |
|
* just side-steps the real bug. |
1326 |
|
* |
1327 |
|
* NOTE: Snapshots of OpenBSD/landisk _after_ 4.1 seem |
1328 |
|
* to work WITHOUT this hack, but NOT with it! |
1329 |
|
*/ |
1330 |
|
cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL); |
1331 |
|
|
1332 |
break; |
break; |
1333 |
|
|
1334 |
|
|
1477 |
case SH4_SCIF_BASE + SCIF_FTDR: |
case SH4_SCIF_BASE + SCIF_FTDR: |
1478 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
1479 |
/* Add to TX fifo: */ |
/* Add to TX fifo: */ |
1480 |
if (d->scif_tx_fifo_cursize >= sizeof( |
if (d->scif_tx_fifo_cursize >= |
1481 |
d->scif_tx_fifo)) { |
sizeof(d->scif_tx_fifo)) { |
1482 |
fatal("[ SCIF TX fifo overrun! ]\n"); |
fatal("[ SCIF TX fifo overrun! ]\n"); |
1483 |
d->scif_tx_fifo_cursize = 0; |
d->scif_tx_fifo_cursize = 0; |
1484 |
} |
} |
1485 |
|
|
1486 |
d->scif_tx_fifo[d->scif_tx_fifo_cursize++] = idata; |
d->scif_tx_fifo[d->scif_tx_fifo_cursize++] = idata; |
1487 |
d->scif_delayed_tx = 2; |
d->scif_delayed_tx = SCIF_DELAYED_TX_VALUE; |
1488 |
} |
} |
1489 |
break; |
break; |
1490 |
|
|
1525 |
break; |
break; |
1526 |
|
|
1527 |
case SH4_SCIF_BASE + SCIF_FDR: |
case SH4_SCIF_BASE + SCIF_FDR: |
1528 |
|
/* Nr of bytes in the TX and RX fifos, respectively: */ |
1529 |
odata = (console_charavail(d->scif_console_handle)? 1 : 0) |
odata = (console_charavail(d->scif_console_handle)? 1 : 0) |
1530 |
+ (d->scif_tx_fifo_cursize << 8); |
+ (d->scif_tx_fifo_cursize << 8); |
1531 |
break; |
break; |
1577 |
(int)relative_addr, (int)idata); |
(int)relative_addr, (int)idata); |
1578 |
} |
} |
1579 |
#ifdef SH4_DEGUG |
#ifdef SH4_DEGUG |
1580 |
// exit(1); |
/* exit(1); */ |
1581 |
#endif |
#endif |
1582 |
} |
} |
1583 |
|
|
1590 |
|
|
1591 |
DEVINIT(sh4) |
DEVINIT(sh4) |
1592 |
{ |
{ |
1593 |
char tmp[200]; |
char tmp[200], n[200]; |
1594 |
|
int i; |
1595 |
struct machine *machine = devinit->machine; |
struct machine *machine = devinit->machine; |
1596 |
struct sh4_data *d = malloc(sizeof(struct sh4_data)); |
struct sh4_data *d = malloc(sizeof(struct sh4_data)); |
1597 |
|
|
1598 |
if (d == NULL) { |
if (d == NULL) { |
1599 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
1600 |
exit(1); |
exit(1); |
1601 |
} |
} |
1602 |
memset(d, 0, sizeof(struct sh4_data)); |
memset(d, 0, sizeof(struct sh4_data)); |
1603 |
|
|
|
d->scif_console_handle = console_start_slave(devinit->machine, |
|
|
"SH4 SCIF", 1); |
|
1604 |
|
|
1605 |
snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]", |
/* |
1606 |
devinit->interrupt_path, SH4_INTEVT_SCIF_RXI); |
* Main SH4 device, and misc memory stuff: |
1607 |
INTERRUPT_CONNECT(tmp, d->scif_rx_irq); |
*/ |
|
snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]", |
|
|
devinit->interrupt_path, SH4_INTEVT_SCIF_TXI); |
|
|
INTERRUPT_CONNECT(tmp, d->scif_tx_irq); |
|
1608 |
|
|
1609 |
memory_device_register(machine->memory, devinit->name, |
memory_device_register(machine->memory, devinit->name, |
1610 |
SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL); |
SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL); |
1615 |
/* 0xe0000000: Store queues: */ |
/* 0xe0000000: Store queues: */ |
1616 |
dev_ram_init(machine, 0xe0000000, 32 * 2, DEV_RAM_RAM, 0x0); |
dev_ram_init(machine, 0xe0000000, 32 * 2, DEV_RAM_RAM, 0x0); |
1617 |
|
|
1618 |
|
|
1619 |
|
/* |
1620 |
|
* SCIF (Serial console): |
1621 |
|
*/ |
1622 |
|
|
1623 |
|
d->scif_console_handle = console_start_slave(devinit->machine, |
1624 |
|
"SH4 SCIF", 1); |
1625 |
|
|
1626 |
|
snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]", |
1627 |
|
devinit->interrupt_path, SH4_INTEVT_SCIF_RXI); |
1628 |
|
INTERRUPT_CONNECT(tmp, d->scif_rx_irq); |
1629 |
|
snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]", |
1630 |
|
devinit->interrupt_path, SH4_INTEVT_SCIF_TXI); |
1631 |
|
INTERRUPT_CONNECT(tmp, d->scif_tx_irq); |
1632 |
|
|
1633 |
|
|
1634 |
/* |
/* |
1635 |
|
* Caches (fake): |
1636 |
|
* |
1637 |
* 0xf0000000 SH4_CCIA I-Cache address array |
* 0xf0000000 SH4_CCIA I-Cache address array |
1638 |
* 0xf1000000 SH4_CCID I-Cache data array |
* 0xf1000000 SH4_CCID I-Cache data array |
1639 |
* 0xf4000000 SH4_CCDA D-Cache address array |
* 0xf4000000 SH4_CCDA D-Cache address array |
1641 |
* |
* |
1642 |
* TODO: Implement more correct cache behaviour? |
* TODO: Implement more correct cache behaviour? |
1643 |
*/ |
*/ |
1644 |
|
|
1645 |
dev_ram_init(machine, SH4_CCIA, SH4_ICACHE_SIZE * 2, DEV_RAM_RAM, 0x0); |
dev_ram_init(machine, SH4_CCIA, SH4_ICACHE_SIZE * 2, DEV_RAM_RAM, 0x0); |
1646 |
dev_ram_init(machine, SH4_CCID, SH4_ICACHE_SIZE, DEV_RAM_RAM, 0x0); |
dev_ram_init(machine, SH4_CCID, SH4_ICACHE_SIZE, DEV_RAM_RAM, 0x0); |
1647 |
dev_ram_init(machine, SH4_CCDA, SH4_DCACHE_SIZE * 2, DEV_RAM_RAM, 0x0); |
dev_ram_init(machine, SH4_CCDA, SH4_DCACHE_SIZE * 2, DEV_RAM_RAM, 0x0); |
1648 |
dev_ram_init(machine, SH4_CCDD, SH4_DCACHE_SIZE, DEV_RAM_RAM, 0x0); |
dev_ram_init(machine, SH4_CCDD, SH4_DCACHE_SIZE, DEV_RAM_RAM, 0x0); |
1649 |
|
|
1650 |
/* 0xf2000000 SH4_ITLB_AA */ |
/* 0xf2000000 SH4_ITLB_AA */ |
1651 |
memory_device_register(machine->memory, devinit->name, SH4_ITLB_AA, |
memory_device_register(machine->memory, "sh4_itlb_aa", SH4_ITLB_AA, |
1652 |
0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL); |
0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL); |
1653 |
|
|
1654 |
/* 0xf3000000 SH4_ITLB_DA1 */ |
/* 0xf3000000 SH4_ITLB_DA1 */ |
1655 |
memory_device_register(machine->memory, devinit->name, SH4_ITLB_DA1, |
memory_device_register(machine->memory, "sh4_itlb_da1", SH4_ITLB_DA1, |
1656 |
0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL); |
0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL); |
1657 |
|
|
1658 |
/* 0xf6000000 SH4_UTLB_AA */ |
/* 0xf6000000 SH4_UTLB_AA */ |
1659 |
memory_device_register(machine->memory, devinit->name, SH4_UTLB_AA, |
memory_device_register(machine->memory, "sh4_utlb_aa", SH4_UTLB_AA, |
1660 |
0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL); |
0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL); |
1661 |
|
|
1662 |
/* 0xf7000000 SH4_UTLB_DA1 */ |
/* 0xf7000000 SH4_UTLB_DA1 */ |
1663 |
memory_device_register(machine->memory, devinit->name, SH4_UTLB_DA1, |
memory_device_register(machine->memory, "sh4_utlb_da1", SH4_UTLB_DA1, |
1664 |
0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL); |
0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL); |
1665 |
|
|
1666 |
|
|
1667 |
|
/* |
1668 |
|
* PCIC (PCI controller) at 0xfe200000: |
1669 |
|
*/ |
1670 |
|
|
1671 |
|
memory_device_register(machine->memory, "sh4_pcic", SH4_PCIC, |
1672 |
|
N_PCIC_REGS * sizeof(uint32_t), dev_sh4_pcic_access, d, |
1673 |
|
DM_DEFAULT, NULL); |
1674 |
|
|
1675 |
|
/* Initial PCI control register contents: */ |
1676 |
|
d->bsc_bcr2 = BCR2_PORTEN; |
1677 |
|
d->pcic_reg[PCIC_REG(SH4_PCICONF2)] = PCI_CLASS_CODE(PCI_CLASS_BRIDGE, |
1678 |
|
PCI_SUBCLASS_BRIDGE_HOST, 0); |
1679 |
|
|
1680 |
|
/* Register 16 PCIC interrupts: */ |
1681 |
|
for (i=0; i<N_PCIC_IRQS; i++) { |
1682 |
|
struct interrupt template; |
1683 |
|
snprintf(n, sizeof(n), "%s.pcic.%i", |
1684 |
|
devinit->interrupt_path, i); |
1685 |
|
memset(&template, 0, sizeof(template)); |
1686 |
|
template.line = i; |
1687 |
|
template.name = n; |
1688 |
|
template.extra = d; |
1689 |
|
template.interrupt_assert = sh4_pcic_interrupt_assert; |
1690 |
|
template.interrupt_deassert = sh4_pcic_interrupt_deassert; |
1691 |
|
interrupt_handler_register(&template); |
1692 |
|
|
1693 |
|
snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]", |
1694 |
|
devinit->interrupt_path, SH4_INTEVT_IRQ0 + 0x20 * i); |
1695 |
|
INTERRUPT_CONNECT(tmp, d->cpu_pcic_interrupt[i]); |
1696 |
|
} |
1697 |
|
|
1698 |
|
/* Register the PCI bus: */ |
1699 |
|
snprintf(tmp, sizeof(tmp), "%s.pcic", devinit->interrupt_path); |
1700 |
|
d->pci_data = bus_pci_init( |
1701 |
|
devinit->machine, |
1702 |
|
tmp, /* pciirq */ |
1703 |
|
0, /* pci device io offset */ |
1704 |
|
0, /* pci device mem offset */ |
1705 |
|
SH4_PCIC_IO, /* PCI portbase */ |
1706 |
|
SH4_PCIC_MEM, /* PCI membase */ |
1707 |
|
tmp, /* PCI irqbase */ |
1708 |
|
0x00000000, /* ISA portbase */ |
1709 |
|
0x00000000, /* ISA membase */ |
1710 |
|
"TODOisaIrqBase"); /* ISA irqbase */ |
1711 |
|
|
1712 |
|
/* Return PCI bus pointer, to allow per-machine devices |
1713 |
|
to be added later: */ |
1714 |
|
devinit->return_ptr = d->pci_data; |
1715 |
|
|
1716 |
|
|
1717 |
|
/* |
1718 |
|
* Timer: |
1719 |
|
*/ |
1720 |
|
|
1721 |
d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d); |
d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d); |
1722 |
machine_add_tickfunction(devinit->machine, dev_sh4_tick, d, |
machine_add_tickfunction(devinit->machine, dev_sh4_tick, d, |
1723 |
SH4_TICK_SHIFT, 0.0); |
SH4_TICK_SHIFT, 0.0); |
1746 |
exit(1); |
exit(1); |
1747 |
} |
} |
1748 |
|
|
1749 |
|
|
1750 |
/* |
/* |
1751 |
* Bus State Controller initial values, according to the |
* Bus State Controller initial values, according to the |
1752 |
* SH7760 manual: |
* SH7760 manual: |
1753 |
*/ |
*/ |
1754 |
|
|
1755 |
d->bsc_bcr2 = 0x3ffc; |
d->bsc_bcr2 = 0x3ffc; |
1756 |
d->bsc_wcr1 = 0x77777777; |
d->bsc_wcr1 = 0x77777777; |
1757 |
d->bsc_wcr2 = 0xfffeefff; |
d->bsc_wcr2 = 0xfffeefff; |
1758 |
|
|
1759 |
|
|
1760 |
return 1; |
return 1; |
1761 |
} |
} |
1762 |
|
|