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dpavlin |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_pcic.c,v 1.14 2005/11/13 00:14:09 debug Exp $ |
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dpavlin |
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* |
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* Intel 82365SL PC Card Interface Controller (called "pcic" by NetBSD). |
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* |
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dpavlin |
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* TODO: Lots of stuff. This is just a quick hack. Don't rely on it. |
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dpavlin |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "cpu.h" |
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#include "device.h" |
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#include "emul.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "i82365reg.h" |
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#include "pcmciareg.h" |
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/* #define debug fatal */ |
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#define DEV_PCIC_LENGTH 2 |
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struct pcic_data { |
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int irq_nr; |
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int regnr; |
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}; |
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/* |
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* dev_pcic_cis_access(): |
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*/ |
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int dev_pcic_cis_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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/* struct pcic_data *d = (struct pcic_data *) extra; */ |
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uint64_t idata = 0, odata = 0; |
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idata = memory_readmax64(cpu, data, len); |
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{ |
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#if 0 |
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/* SMC, PCM Ethernet Adapter, CIS V1.05 (manufacturer 0x108, |
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product 0x105) */ |
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unsigned char x[] = { |
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PCMCIA_CISTPL_DEVICE, 3, PCMCIA_DTYPE_FUNCSPEC, 0xff,0xff, |
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PCMCIA_CISTPL_FUNCID, 2, 0x06, 0x00, |
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PCMCIA_CISTPL_MANFID, 4, 0x08, 0x01, 0x05, 0x01, |
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PCMCIA_CISTPL_VERS_1, 0x26, |
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0x04, 0x01, 0x53, 0x4d, 0x43, 0x00, 0x50, 0x43, 0x4d, 0x20, |
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0x45, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x20, 0x41, |
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0x64, 0x61, 0x70, 0x74, 0x65, 0x72, 0x00, 0x43, 0x49, 0x53, |
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0x20, 0x56, 0x31, 0x2e, 0x30, 0x35, 0x00, 0xff, |
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PCMCIA_CISTPL_CONFIG, 0x0a, |
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0x02, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0xff, |
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PCMCIA_CISTPL_CFTABLE_ENTRY, 0x0b, |
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0xc1, 0x01, 0x70, 0x50, 0xbc, 0x8e, 0x48, 0x40, 0x00,0x02,0xff, |
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/* unhandled CISTPL 22 */ |
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0x22, 0x02, 0x01, 0x02, |
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/* unhandled CISTPL 22 */ |
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0x22, 0x05, 0x02, 0x80, 0x96, 0x98, 0x00, |
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/* unhandled CISTPL 22 */ |
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0x22, 0x02, 0x03, 0x01, |
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/* unhandled CISTPL 22 */ |
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0x22, 0x08, 0x04, 0x06, 0x00, 0x00, 0xc0, 0x2f, 0x48, 0xd2, |
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/* unhandled CISTPL 22 */ |
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0x22, 0x02, 0x05, 0x01, |
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PCMCIA_CISTPL_END, 0 |
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}; |
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#endif |
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/* From http://www.mail-archive.com/freebsd-current@freebsd. |
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org/msg32550.html */ |
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unsigned char x[] = { |
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PCMCIA_CISTPL_DEVICE, 3, 0xdc, 0x00, 0xff, |
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PCMCIA_CISTPL_VERS_1, 0x1a, |
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0x04,0x01,0x20,0x00,0x4e,0x69,0x6e,0x6a,0x61,0x41,0x54,0x41, |
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0x2d,0x00,0x56,0x31,0x2e,0x30,0x00,0x41,0x50,0x30,0x30,0x20, |
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0x00,0xff, |
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PCMCIA_CISTPL_CONFIG, 5, |
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0x01,0x23,0x00,0x02,0x03, |
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PCMCIA_CISTPL_CFTABLE_ENTRY, 0x15, |
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0xe1,0x01,0x3d,0x11,0x55,0x1e,0xfc,0x23,0xf0,0x61,0x80,0x01, |
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0x07,0x86,0x03,0x01,0x30,0x68,0xd0,0x10,0x00, |
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#if 0 |
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PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf, |
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0x22,0x38,0xf0,0x61,0x90,0x01,0x07,0x96,0x03,0x01,0x30,0x68, |
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0xd0,0x10,0x00, |
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PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf, |
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0x23,0x38,0xf0,0x61,0xa0,0x01,0x07,0xa6,0x03,0x01,0x30,0x68, |
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0xd0,0x10,0x00, |
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#endif |
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PCMCIA_CISTPL_NO_LINK, 0, |
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PCMCIA_CISTPL_END, 0 |
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}; |
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relative_addr /= 2; |
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if (relative_addr < sizeof(x)) |
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odata = x[relative_addr]; |
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dpavlin |
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debug("[ dev_pcic_cis_access: blah blah: addr=0x%x ]\n", |
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(int)relative_addr); |
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dpavlin |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* dev_pcic_access(): |
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*/ |
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int dev_pcic_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct pcic_data *d = (struct pcic_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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int controller_nr, socket_nr; |
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dpavlin |
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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dpavlin |
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controller_nr = d->regnr & 0x80? 1 : 0; |
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socket_nr = d->regnr & 0x40? 1 : 0; |
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switch (relative_addr) { |
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case 0: /* Register select: */ |
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if (writeflag == MEM_WRITE) |
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d->regnr = idata; |
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else |
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odata = d->regnr; |
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break; |
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case 1: /* Register access: */ |
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switch (d->regnr & 0x3f) { |
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case PCIC_IDENT: |
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/* This causes sockets A and B to be present on |
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controller 0, and only socket A on controller 1. */ |
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if (controller_nr == 1 && socket_nr == 1) |
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odata = 0; |
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else |
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odata = PCIC_IDENT_IFTYPE_MEM_AND_IO |
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| PCIC_IDENT_REV_I82365SLR1; |
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break; |
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#if 1 |
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case PCIC_INTR: |
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odata = PCIC_INTR_IRQ3; |
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break; |
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#endif |
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case PCIC_CSC: |
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odata = PCIC_CSC_GPI; |
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break; |
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case PCIC_IF_STATUS: |
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dpavlin |
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odata = PCIC_IF_STATUS_READY |
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| PCIC_IF_STATUS_POWERACTIVE; |
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dpavlin |
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if (controller_nr == 0 && socket_nr == 0) |
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odata |= PCIC_IF_STATUS_CARDDETECT_PRESENT; |
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break; |
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default: |
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if (writeflag == MEM_WRITE) { |
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debug("[ pcic: unimplemented write to " |
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"controller %i socket %c, regnr %i: " |
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"data=0x%02x ]\n", controller_nr, |
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socket_nr? 'B' : 'A', |
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d->regnr & 0x3f, (int)idata); |
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} else { |
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debug("[ pcic: unimplemented read from " |
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"controller %i socket %c, regnr %i ]\n", |
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controller_nr, socket_nr? 'B' : 'A', |
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d->regnr & 0x3f); |
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} |
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} |
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} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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return 1; |
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} |
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/* |
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* devinit_pcic(): |
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*/ |
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int devinit_pcic(struct devinit *devinit) |
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{ |
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struct pcic_data *d = malloc(sizeof(struct pcic_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct pcic_data)); |
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d->irq_nr = devinit->irq_nr; |
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_PCIC_LENGTH, |
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dpavlin |
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dev_pcic_access, (void *)d, DM_DEFAULT, NULL); |
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dpavlin |
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/* TODO: this shouldn't be hardcoded for hpcmips here! */ |
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memory_device_register(devinit->machine->memory, "pcic_cis", |
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0x10070000, 0x1000, dev_pcic_cis_access, (void *)d, |
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dpavlin |
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DM_DEFAULT, NULL); |
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dpavlin |
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/* TODO: find out a good way to specify the address, and the IRQ! */ |
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dpavlin |
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/* IRQ 8 + 32 + 9 */ |
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device_add(devinit->machine, "wdc addr=0x14000180 irq=49"); |
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dpavlin |
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/* TODO: Linux/MobilePro looks at 0x14000170 and 0x1f0... */ |
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/* Yuck. Now there are two. How should this be solved nicely? */ |
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dpavlin |
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device_add(devinit->machine, "wdc addr=0x140001f0 irq=49"); |
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dpavlin |
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return 1; |
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} |
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