24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* $Id: dev_gc.c,v 1.14 2007/09/11 21:42:52 debug Exp $ |
* $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $ |
28 |
* |
* |
29 |
* COMMENT: Grand Central Interrupt controller (used by MacPPC) |
* COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc) |
30 |
|
* based on dev_gc.c |
31 |
*/ |
*/ |
32 |
|
|
33 |
#include <stdio.h> |
#include <stdio.h> |
41 |
#include "misc.h" |
#include "misc.h" |
42 |
|
|
43 |
|
|
44 |
#define DEV_GC_LENGTH 0x100 |
#define DEV_OPENPIC_LENGTH 0x40000 |
45 |
|
|
46 |
struct gc_data { |
struct openpic_data { |
47 |
struct interrupt cpu_irq; |
struct interrupt cpu_irq; |
48 |
|
|
49 |
uint32_t status_hi; |
uint32_t status_hi; |
53 |
}; |
}; |
54 |
|
|
55 |
|
|
56 |
void gc_hi_interrupt_assert(struct interrupt *interrupt) |
void openpic_hi_interrupt_assert(struct interrupt *interrupt) |
57 |
{ |
{ |
58 |
struct gc_data *d = interrupt->extra; |
struct openpic_data *d = interrupt->extra; |
59 |
d->status_hi |= interrupt->line; |
d->status_hi |= interrupt->line; |
60 |
if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
61 |
INTERRUPT_ASSERT(d->cpu_irq); |
INTERRUPT_ASSERT(d->cpu_irq); |
62 |
} |
} |
63 |
void gc_hi_interrupt_deassert(struct interrupt *interrupt) |
void openpic_hi_interrupt_deassert(struct interrupt *interrupt) |
64 |
{ |
{ |
65 |
struct gc_data *d = interrupt->extra; |
struct openpic_data *d = interrupt->extra; |
66 |
d->status_hi &= ~interrupt->line; |
d->status_hi &= ~interrupt->line; |
67 |
if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
68 |
INTERRUPT_DEASSERT(d->cpu_irq); |
INTERRUPT_DEASSERT(d->cpu_irq); |
69 |
} |
} |
70 |
void gc_lo_interrupt_assert(struct interrupt *interrupt) |
void openpic_lo_interrupt_assert(struct interrupt *interrupt) |
71 |
{ |
{ |
72 |
struct gc_data *d = interrupt->extra; |
struct openpic_data *d = interrupt->extra; |
73 |
d->status_lo |= interrupt->line; |
d->status_lo |= interrupt->line; |
74 |
if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
75 |
INTERRUPT_ASSERT(d->cpu_irq); |
INTERRUPT_ASSERT(d->cpu_irq); |
76 |
} |
} |
77 |
void gc_lo_interrupt_deassert(struct interrupt *interrupt) |
void openpic_lo_interrupt_deassert(struct interrupt *interrupt) |
78 |
{ |
{ |
79 |
struct gc_data *d = interrupt->extra; |
struct openpic_data *d = interrupt->extra; |
80 |
d->status_lo &= ~interrupt->line; |
d->status_lo &= ~interrupt->line; |
81 |
if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
82 |
INTERRUPT_DEASSERT(d->cpu_irq); |
INTERRUPT_DEASSERT(d->cpu_irq); |
83 |
} |
} |
84 |
|
|
85 |
|
/* |
86 |
|
* FIXME acitvity is never sat |
87 |
|
*/ |
88 |
|
|
89 |
|
#define OPENPIC_MASK 0x80000000 |
90 |
|
#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ |
91 |
|
#define OPENPIC_PRIORITY_MASK 0x000f0000 |
92 |
|
#define OPENPIC_PRIORITY_SHIFT 16 |
93 |
|
#define OPENPIC_VECTOR_MASK 0x000000ff |
94 |
|
|
95 |
|
#define OPENPIC_VEC_TIMER 64 /* and up */ |
96 |
|
#define OPENPIC_VEC_IPI 72 /* and up */ |
97 |
|
#define OPENPIC_VEC_SPURIOUS 127 |
98 |
|
|
99 |
|
#define OPENPIC_NUM_TIMERS 4 |
100 |
|
#define OPENPIC_NUM_IPI 4 |
101 |
|
#define OPENPIC_NUM_PRI 16 |
102 |
|
#define OPENPIC_NUM_VECTORS 256 |
103 |
|
|
104 |
DEVICE_ACCESS(gc) |
DEVICE_ACCESS(openpic) |
105 |
{ |
{ |
106 |
struct gc_data *d = extra; |
// struct openpic_data *d = extra; |
107 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
108 |
|
|
109 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
110 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
111 |
|
// shuffle byte order |
112 |
|
idata = |
113 |
|
( idata & 0x000000ff ) << 24 | |
114 |
|
( idata & 0x0000ff00 ) << 8 | |
115 |
|
( idata & 0x00ff0000 ) >> 8 | |
116 |
|
( idata & 0xff000000 ) >> 24 ; |
117 |
|
|
118 |
|
uint64_t priority,vector, active; |
119 |
|
priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT; |
120 |
|
vector = ( idata & OPENPIC_VECTOR_MASK ); |
121 |
|
active = ( idata & OPENPIC_ACTIVITY ); |
122 |
|
|
123 |
|
debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n", |
124 |
|
(int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active ); |
125 |
|
} |
126 |
|
|
127 |
switch (relative_addr) { |
switch (relative_addr) { |
128 |
|
|
129 |
|
// version |
130 |
|
case 0x00: |
131 |
|
if (writeflag == MEM_READ) { |
132 |
|
// version 1.x, so 2 -> 1.2 |
133 |
|
odata = 2; |
134 |
|
debug("[ openpic: read version " |
135 |
|
"offset 0x%x = 1.%d]\n", (int) |
136 |
|
relative_addr, (int)odata); |
137 |
|
odata |= 0x00190000; // FIXME ? |
138 |
|
|
139 |
|
} |
140 |
|
fatal("[ openpic: unimplemented write to " |
141 |
|
"offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int) |
142 |
|
relative_addr, (int)idata); |
143 |
|
break; |
144 |
|
|
145 |
|
// global timer frequency |
146 |
|
case 0xf0: |
147 |
|
if (writeflag == MEM_READ) { |
148 |
|
// this would be correct, but real DSM-G600 isn't |
149 |
|
// returning it! |
150 |
|
//odata = 170 * 1000000; // MHz |
151 |
|
odata = 0; |
152 |
|
debug("[ openpic: read global timer frequency " |
153 |
|
"offset 0x%x = %x]\n", (int) |
154 |
|
relative_addr, (int)odata); |
155 |
|
} |
156 |
|
fatal("[ openpic: unimplemented write to " |
157 |
|
"offset 0x%x: data=0x%x ]\n", (int) |
158 |
|
relative_addr, (int)idata); |
159 |
|
break; |
160 |
|
|
161 |
#if 0 |
#if 0 |
162 |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
#define INT_STATE_REG_H (interrupt_reg + 0x00) |
163 |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
#define INT_ENABLE_REG_H (interrupt_reg + 0x04) |
167 |
#define INT_ENABLE_REG_L (interrupt_reg + 0x14) |
#define INT_ENABLE_REG_L (interrupt_reg + 0x14) |
168 |
#define INT_CLEAR_REG_L (interrupt_reg + 0x18) |
#define INT_CLEAR_REG_L (interrupt_reg + 0x18) |
169 |
#define INT_LEVEL_REG_L (interrupt_reg + 0x1c) |
#define INT_LEVEL_REG_L (interrupt_reg + 0x1c) |
|
#endif |
|
170 |
|
|
171 |
case 0x10: |
case 0x10: |
172 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
254 |
case 0x2c: |
case 0x2c: |
255 |
/* Avoid a debug message. */ |
/* Avoid a debug message. */ |
256 |
break; |
break; |
257 |
|
#endif |
258 |
default:if (writeflag == MEM_WRITE) { |
default: |
259 |
fatal("[ gc: unimplemented write to " |
if (writeflag == MEM_WRITE) { |
260 |
"offset 0x%x: data=0x%x ]\n", (int) |
fatal("[ openpic: unimplemented write to " |
261 |
relative_addr, (int)idata); |
"offset 0x%x idata = %x ]\n", |
262 |
|
(int)relative_addr, (int)idata |
263 |
|
); |
264 |
} else { |
} else { |
265 |
fatal("[ gc: unimplemented read from " |
// decoded from real device |
266 |
"offset 0x%x ]\n", (int)relative_addr); |
odata |= OPENPIC_MASK; |
267 |
|
|
268 |
|
int vec = |
269 |
|
( |
270 |
|
( |
271 |
|
( |
272 |
|
( |
273 |
|
( relative_addr - 0x120 ) & 0xfff |
274 |
|
) / 0x40 |
275 |
|
) |
276 |
|
) & 0xff |
277 |
|
) + 0x40; |
278 |
|
|
279 |
|
odata |= vec; |
280 |
|
|
281 |
|
debug("[ openpic: unimplemented read from " |
282 |
|
"offset 0x%x decoded vec = 0x%02x %d odata = %x ]\n", |
283 |
|
(int)relative_addr, vec, vec, (int)odata |
284 |
|
); |
285 |
} |
} |
286 |
} |
} |
287 |
|
|
288 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) { |
289 |
|
|
290 |
|
debug("[ openpic: READ %05x | %08x ]\n", |
291 |
|
(int)relative_addr, (int)odata |
292 |
|
); |
293 |
|
|
294 |
|
// shuffle byte order |
295 |
|
odata = |
296 |
|
( odata & 0x000000ff ) << 24 | |
297 |
|
( odata & 0x0000ff00 ) << 8 | |
298 |
|
( odata & 0x00ff0000 ) >> 8 | |
299 |
|
( odata & 0xff000000 ) >> 24 ; |
300 |
memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len, odata); |
301 |
|
} |
302 |
|
|
303 |
return 1; |
return 1; |
304 |
} |
} |
305 |
|
|
306 |
|
|
307 |
DEVINIT(gc) |
DEVINIT(openpic) |
308 |
{ |
{ |
309 |
struct gc_data *d; |
struct openpic_data *d; |
310 |
int i; |
int i; |
311 |
|
|
312 |
CHECK_ALLOCATION(d = malloc(sizeof(struct gc_data))); |
CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data))); |
313 |
memset(d, 0, sizeof(struct gc_data)); |
memset(d, 0, sizeof(struct openpic_data)); |
314 |
|
|
315 |
/* Connect to the CPU interrupt pin: */ |
/* Connect to the CPU interrupt pin: */ |
316 |
INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq); |
INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq); |
317 |
|
|
318 |
/* |
/* |
319 |
* Register the 64 Grand Central interrupts (32 lo, 32 hi): |
* Register the 126 OpenPIC interrupts |
320 |
*/ |
*/ |
321 |
for (i=0; i<32; i++) { |
for (i=0; i<126; i++) { |
322 |
struct interrupt template; |
struct interrupt template; |
323 |
char n[300]; |
char n[300]; |
324 |
snprintf(n, sizeof(n), "%s.gc.lo.%i", |
snprintf(n, sizeof(n), "%s.openpic.%i", |
|
devinit->interrupt_path, i); |
|
|
memset(&template, 0, sizeof(template)); |
|
|
template.line = 1 << i; |
|
|
template.name = n; |
|
|
template.extra = d; |
|
|
template.interrupt_assert = gc_lo_interrupt_assert; |
|
|
template.interrupt_deassert = gc_lo_interrupt_deassert; |
|
|
interrupt_handler_register(&template); |
|
|
|
|
|
snprintf(n, sizeof(n), "%s.gc.hi.%i", |
|
325 |
devinit->interrupt_path, i); |
devinit->interrupt_path, i); |
326 |
memset(&template, 0, sizeof(template)); |
memset(&template, 0, sizeof(template)); |
327 |
template.line = 1 << i; |
template.line = 1 << i; |
328 |
template.name = n; |
template.name = n; |
329 |
template.extra = d; |
template.extra = d; |
330 |
template.interrupt_assert = gc_hi_interrupt_assert; |
template.interrupt_assert = openpic_lo_interrupt_assert; |
331 |
template.interrupt_deassert = gc_hi_interrupt_deassert; |
template.interrupt_deassert = openpic_lo_interrupt_deassert; |
332 |
interrupt_handler_register(&template); |
interrupt_handler_register(&template); |
333 |
|
// debug("[ openpic: added interrupt %s ]\n", n); |
334 |
} |
} |
335 |
|
|
336 |
memory_device_register(devinit->machine->memory, "gc", |
memory_device_register(devinit->machine->memory, "openpic", |
337 |
devinit->addr, DEV_GC_LENGTH, dev_gc_access, d, DM_DEFAULT, NULL); |
devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL); |
338 |
|
|
339 |
return 1; |
return 1; |
340 |
} |
} |