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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* $Id: dev_gc.c,v 1.8 2006/02/27 05:32:26 debug Exp $ |
* $Id: dev_gc.c,v 1.12 2007/02/16 17:17:51 debug Exp $ |
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* |
* |
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* Grand Central Interrupt controller (used by MacPPC). |
* Grand Central Interrupt controller (used by MacPPC). |
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*/ |
*/ |
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#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#define DEV_GC_LENGTH 0x100 |
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struct gc_data { |
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struct interrupt cpu_irq; |
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uint32_t status_hi; |
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uint32_t status_lo; |
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uint32_t enable_hi; |
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uint32_t enable_lo; |
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}; |
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void gc_hi_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct gc_data *d = interrupt->extra; |
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d->status_hi |= interrupt->line; |
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if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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void gc_hi_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct gc_data *d = interrupt->extra; |
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d->status_hi &= ~interrupt->line; |
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if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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} |
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void gc_lo_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct gc_data *d = interrupt->extra; |
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d->status_lo |= interrupt->line; |
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if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
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void gc_lo_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct gc_data *d = interrupt->extra; |
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d->status_lo &= ~interrupt->line; |
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if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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} |
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DEVICE_ACCESS(gc) |
DEVICE_ACCESS(gc) |
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{ |
{ |
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struct gc_data *d = extra; |
struct gc_data *d = extra; |
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if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
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odata = d->enable_hi; |
odata = d->enable_hi; |
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else { |
else { |
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uint32_t old_enable_hi = d->enable_hi; |
int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->enable_hi = idata; |
d->enable_hi = idata; |
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if (d->enable_hi != old_enable_hi) |
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cpu_interrupt(cpu, d->reassert_irq); |
new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
} |
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break; |
break; |
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case 0x18: |
case 0x18: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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uint32_t old_status_hi = d->status_hi; |
int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->status_hi &= ~idata; |
d->status_hi &= ~idata; |
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if (d->status_hi != old_status_hi) |
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cpu_interrupt(cpu, d->reassert_irq); |
new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
} |
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break; |
break; |
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if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
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odata = d->enable_lo; |
odata = d->enable_lo; |
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else { |
else { |
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uint32_t old_enable_lo = d->enable_lo; |
int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->enable_lo = idata; |
d->enable_lo = idata; |
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if (d->enable_lo != old_enable_lo) |
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cpu_interrupt(cpu, d->reassert_irq); |
new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
} |
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break; |
break; |
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case 0x28: |
case 0x28: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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uint32_t old_status_lo = d->status_lo; |
int old_assert = (d->status_lo & d->enable_lo |
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|| d->status_hi & d->enable_hi); |
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int new_assert; |
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d->status_lo &= ~idata; |
d->status_lo &= ~idata; |
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if (d->status_lo != old_status_lo) |
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cpu_interrupt(cpu, d->reassert_irq); |
new_assert = (d->status_lo & d->enable_lo || |
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d->status_hi & d->enable_hi); |
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if (old_assert && !new_assert) |
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INTERRUPT_DEASSERT(d->cpu_irq); |
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else if (!old_assert && new_assert) |
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INTERRUPT_ASSERT(d->cpu_irq); |
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} |
} |
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break; |
break; |
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case 0x2c: |
case 0x2c: |
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/* Avoir a debug message. */ |
/* Avoid a debug message. */ |
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break; |
break; |
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default:if (writeflag == MEM_WRITE) { |
default:if (writeflag == MEM_WRITE) { |
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} |
} |
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/* |
DEVINIT(gc) |
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* dev_gc_init(): |
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*/ |
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struct gc_data *dev_gc_init(struct machine *machine, struct memory *mem, |
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uint64_t addr, int reassert_irq) |
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{ |
{ |
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struct gc_data *d; |
struct gc_data *d; |
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int i; |
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d = malloc(sizeof(struct gc_data)); |
d = malloc(sizeof(struct gc_data)); |
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if (d == NULL) { |
if (d == NULL) { |
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exit(1); |
exit(1); |
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} |
} |
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memset(d, 0, sizeof(struct gc_data)); |
memset(d, 0, sizeof(struct gc_data)); |
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d->reassert_irq = reassert_irq; |
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memory_device_register(mem, "gc", addr, 0x100, |
/* Connect to the CPU: */ |
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dev_gc_access, d, DM_DEFAULT, NULL); |
INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq); |
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return d; |
/* |
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* Register the 64 Grand Central interrupts (32 lo, 32 hi): |
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*/ |
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for (i=0; i<32; i++) { |
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struct interrupt template; |
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char n[300]; |
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snprintf(n, sizeof(n), "%s.gc.lo.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = gc_lo_interrupt_assert; |
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template.interrupt_deassert = gc_lo_interrupt_deassert; |
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interrupt_handler_register(&template); |
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snprintf(n, sizeof(n), "%s.gc.hi.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = gc_hi_interrupt_assert; |
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template.interrupt_deassert = gc_hi_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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memory_device_register(devinit->machine->memory, "gc", |
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devinit->addr, DEV_GC_LENGTH, dev_gc_access, d, DM_DEFAULT, NULL); |
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return 1; |
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} |
} |
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