92 |
#define OPENPIC_VEC_IPI 72 /* and up */ |
#define OPENPIC_VEC_IPI 72 /* and up */ |
93 |
#define OPENPIC_VEC_SPURIOUS 127 |
#define OPENPIC_VEC_SPURIOUS 127 |
94 |
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95 |
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#define OPENPIC_NUM_TIMERS 4 |
96 |
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#define OPENPIC_NUM_IPI 4 |
97 |
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#define OPENPIC_NUM_PRI 16 |
98 |
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#define OPENPIC_NUM_VECTORS 256 |
99 |
|
|
100 |
DEVICE_ACCESS(openpic) |
DEVICE_ACCESS(openpic) |
101 |
{ |
{ |
102 |
// struct openpic_data *d = extra; |
// struct openpic_data *d = extra; |
103 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0, decoded = 0; |
104 |
|
|
105 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
106 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
107 |
|
decoded = |
108 |
uint64_t priority,vector, active; |
( idata & 0x000000ff ) << 24 | |
109 |
priority = ( relative_addr & 0xf000 ); |
( idata & 0x0000ff00 ) << 8 | |
110 |
vector = ( relative_addr & 0x00ff ); |
( idata & 0x00ff0000 ) >> 8 | |
111 |
active = ( relative_addr & 0x4000 ); |
( idata & 0xff000000 ) >> 24 ; |
112 |
|
|
113 |
debug("[ openpic: access at %04x -> priority: %x vector: 0x%02x %d active: %x ]\n", |
uint64_t priority,vector, active; |
114 |
(int)relative_addr, (int)priority, (int)vector, (int)vector, (int)active ); |
priority = ( decoded & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT; |
115 |
|
vector = ( decoded & OPENPIC_VECTOR_MASK ); |
116 |
|
active = ( decoded & OPENPIC_ACTIVITY ); |
117 |
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|
118 |
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debug("[ openpic: WRITE %05x | %08x => %08x | priority: %x vector: 0x%02x %d active: %x ]\n", |
119 |
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(int)relative_addr, (int)idata, (int)decoded, (int)priority, (int)vector, (int)vector, (int)active ); |
120 |
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} |
121 |
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|
122 |
switch (relative_addr) { |
switch (relative_addr) { |
123 |
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|
143 |
#define INT_ENABLE_REG_L (interrupt_reg + 0x14) |
#define INT_ENABLE_REG_L (interrupt_reg + 0x14) |
144 |
#define INT_CLEAR_REG_L (interrupt_reg + 0x18) |
#define INT_CLEAR_REG_L (interrupt_reg + 0x18) |
145 |
#define INT_LEVEL_REG_L (interrupt_reg + 0x1c) |
#define INT_LEVEL_REG_L (interrupt_reg + 0x1c) |
|
#endif |
|
146 |
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#if 0 |
|
147 |
case 0x10: |
case 0x10: |
148 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
149 |
odata = d->status_hi & d->enable_hi; |
odata = d->status_hi & d->enable_hi; |