25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_ns16550.c,v 1.42 2005/10/26 14:37:04 debug Exp $ |
* $Id: dev_ns16550.c,v 1.46 2005/11/23 18:16:42 debug Exp $ |
29 |
* |
* |
30 |
* NS16550 serial controller. |
* NS16550 serial controller. |
31 |
* |
* |
62 |
|
|
63 |
unsigned char reg[DEV_NS16550_LENGTH]; |
unsigned char reg[DEV_NS16550_LENGTH]; |
64 |
unsigned char fcr; /* FIFO control register */ |
unsigned char fcr; /* FIFO control register */ |
65 |
|
int int_asserted; |
66 |
int dlab; /* Divisor Latch Access bit */ |
int dlab; /* Divisor Latch Access bit */ |
67 |
int divisor; |
int divisor; |
68 |
|
|
94 |
if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) || |
if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) || |
95 |
((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) { |
((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) { |
96 |
d->reg[com_iir] &= ~IIR_NOPEND; |
d->reg[com_iir] &= ~IIR_NOPEND; |
97 |
if (d->reg[com_mcr] & MCR_IENABLE) |
if (d->reg[com_mcr] & MCR_IENABLE) { |
98 |
cpu_interrupt(cpu, d->irqnr); |
cpu_interrupt(cpu, d->irqnr); |
99 |
|
d->int_asserted = 1; |
100 |
|
} |
101 |
} else { |
} else { |
102 |
d->reg[com_iir] |= IIR_NOPEND; |
d->reg[com_iir] |= IIR_NOPEND; |
103 |
cpu_interrupt_ack(cpu, d->irqnr); |
if (d->int_asserted) |
104 |
|
cpu_interrupt_ack(cpu, d->irqnr); |
105 |
|
d->int_asserted = 0; |
106 |
} |
} |
107 |
} |
} |
108 |
|
|
121 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
122 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
123 |
|
|
124 |
|
#if 0 |
125 |
/* The NS16550 should be accessed using byte read/writes: */ |
/* The NS16550 should be accessed using byte read/writes: */ |
126 |
if (len != 1) |
if (len != 1) |
127 |
fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n", |
fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n", |
128 |
d->name, len, (long long)idata); |
d->name, len, (long long)idata); |
129 |
|
#endif |
130 |
|
|
131 |
/* |
/* |
132 |
* Always ready to transmit: |
* Always ready to transmit: |
166 |
|
|
167 |
/* Read/write of data: */ |
/* Read/write of data: */ |
168 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
169 |
if (d->reg[com_mcr] & MCR_LOOPBACK) |
if (d->reg[com_mcr] & MCR_LOOPBACK) { |
170 |
console_makeavail(d->console_handle, idata); |
console_makeavail(d->console_handle, idata); |
171 |
else |
} else { |
172 |
console_putchar(d->console_handle, idata); |
console_putchar(d->console_handle, idata); |
173 |
|
if (console_are_slaves_allowed()) |
174 |
|
d->in_use = 1; |
175 |
|
} |
176 |
d->reg[com_iir] |= IIR_TXRDY; |
d->reg[com_iir] |= IIR_TXRDY; |
177 |
} else { |
} else { |
178 |
if (d->in_use) |
if (d->in_use) |
365 |
|
|
366 |
memory_device_register(devinit->machine->memory, name, devinit->addr, |
memory_device_register(devinit->machine->memory, name, devinit->addr, |
367 |
DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d, |
DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d, |
368 |
MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
369 |
machine_add_tickfunction(devinit->machine, |
machine_add_tickfunction(devinit->machine, |
370 |
dev_ns16550_tick, d, TICK_SHIFT); |
dev_ns16550_tick, d, TICK_SHIFT); |
371 |
|
|