25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_cpc700.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
* $Id: dev_mpc40x.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
29 |
* |
* |
30 |
* COMMENT: IBM CPC700 bridge (PCI and interrupt controller) |
* COMMENT: IBM MPC40X bridge (PCI and interrupt controller) |
31 |
*/ |
*/ |
32 |
|
|
33 |
#include <stdio.h> |
#include <stdio.h> |
42 |
#include "memory.h" |
#include "memory.h" |
43 |
#include "misc.h" |
#include "misc.h" |
44 |
|
|
45 |
#include "cpc700reg.h" |
#include "mpc40xreg.h" |
46 |
|
|
47 |
|
|
48 |
struct cpc700_data { |
struct mpc40x_data { |
49 |
struct interrupt ppc_irq; /* Connected to the CPU */ |
struct interrupt ppc_irq; /* Connected to the CPU */ |
50 |
|
|
51 |
uint32_t sr; /* Interrupt Status register */ |
uint32_t sr; /* Interrupt Status register */ |
55 |
}; |
}; |
56 |
|
|
57 |
|
|
58 |
void cpc700_interrupt_assert(struct interrupt *interrupt) |
void mpc40x_interrupt_assert(struct interrupt *interrupt) |
59 |
{ |
{ |
60 |
struct cpc700_data *d = interrupt->extra; |
struct mpc40x_data *d = interrupt->extra; |
61 |
d->sr |= interrupt->line; |
d->sr |= interrupt->line; |
62 |
if (d->sr & d->er) |
if (d->sr & d->er) |
63 |
INTERRUPT_ASSERT(d->ppc_irq); |
INTERRUPT_ASSERT(d->ppc_irq); |
64 |
} |
} |
65 |
void cpc700_interrupt_deassert(struct interrupt *interrupt) |
void mpc40x_interrupt_deassert(struct interrupt *interrupt) |
66 |
{ |
{ |
67 |
struct cpc700_data *d = interrupt->extra; |
struct mpc40x_data *d = interrupt->extra; |
68 |
d->sr &= ~interrupt->line; |
d->sr &= ~interrupt->line; |
69 |
if (!(d->sr & d->er)) |
if (!(d->sr & d->er)) |
70 |
INTERRUPT_DEASSERT(d->ppc_irq); |
INTERRUPT_DEASSERT(d->ppc_irq); |
72 |
|
|
73 |
|
|
74 |
/* |
/* |
75 |
* dev_cpc700_pci_access(): |
* dev_mpc40x_pci_access(): |
76 |
* |
* |
77 |
* Passes PCI indirect addr and data accesses onto bus_pci. |
* Passes PCI indirect addr and data accesses onto bus_pci. |
78 |
*/ |
*/ |
79 |
DEVICE_ACCESS(cpc700_pci) |
DEVICE_ACCESS(mpc40x_pci) |
80 |
{ |
{ |
81 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
82 |
int bus, dev, func, reg; |
int bus, dev, func, reg; |
83 |
struct cpc700_data *d = extra; |
struct mpc40x_data *d = extra; |
84 |
|
|
85 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
86 |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
105 |
|
|
106 |
|
|
107 |
/* |
/* |
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* dev_cpc700_int_access(): |
* dev_mpc40x_int_access(): |
109 |
* |
* |
110 |
* The interrupt controller. |
* The interrupt controller. |
111 |
*/ |
*/ |
112 |
DEVICE_ACCESS(cpc700_int) |
DEVICE_ACCESS(mpc40x_int) |
113 |
{ |
{ |
114 |
struct cpc700_data *d = extra; |
struct mpc40x_data *d = extra; |
115 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
116 |
|
|
117 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
119 |
|
|
120 |
switch (relative_addr) { |
switch (relative_addr) { |
121 |
|
|
122 |
case CPC_UIC_SR: |
case MPC_UIC_SR: |
123 |
/* Status register (cleared by writing ones): */ |
/* Status register (cleared by writing ones): */ |
124 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
125 |
odata = d->sr; |
odata = d->sr; |
130 |
} |
} |
131 |
break; |
break; |
132 |
|
|
133 |
case CPC_UIC_SRS: |
case MPC_UIC_SRS: |
134 |
/* Status register set: */ |
/* Status register set: */ |
135 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
136 |
fatal("[ cpc700_int: read from CPC_UIC_SRS? ]\n"); |
fatal("[ mpc40x_int: read from MPC_UIC_SRS? ]\n"); |
137 |
odata = d->sr; |
odata = d->sr; |
138 |
} else { |
} else { |
139 |
d->sr = idata; |
d->sr = idata; |
144 |
} |
} |
145 |
break; |
break; |
146 |
|
|
147 |
case CPC_UIC_ER: |
case MPC_UIC_ER: |
148 |
/* Enable register: */ |
/* Enable register: */ |
149 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
150 |
odata = d->er; |
odata = d->er; |
157 |
} |
} |
158 |
break; |
break; |
159 |
|
|
160 |
case CPC_UIC_MSR: |
case MPC_UIC_MSR: |
161 |
/* Masked status: */ |
/* Masked status: */ |
162 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
163 |
odata = d->sr & d->er; |
odata = d->sr & d->er; |
164 |
} else { |
} else { |
165 |
fatal("[ cpc700_int: write to CPC_UIC_MSR? ]\n"); |
fatal("[ mpc40x_int: write to MPC_UIC_MSR? ]\n"); |
166 |
} |
} |
167 |
break; |
break; |
168 |
|
|
169 |
default:if (writeflag == MEM_WRITE) { |
default:if (writeflag == MEM_WRITE) { |
170 |
fatal("[ cpc700_int: unimplemented write to " |
fatal("[ mpc40x_int: unimplemented write to " |
171 |
"offset 0x%x: data=0x%x ]\n", (int) |
"offset 0x%x: data=0x%x ]\n", (int) |
172 |
relative_addr, (int)idata); |
relative_addr, (int)idata); |
173 |
} else { |
} else { |
174 |
fatal("[ cpc700_int: unimplemented read from " |
fatal("[ mpc40x_int: unimplemented read from " |
175 |
"offset 0x%x ]\n", (int)relative_addr); |
"offset 0x%x ]\n", (int)relative_addr); |
176 |
} |
} |
177 |
} |
} |
183 |
} |
} |
184 |
|
|
185 |
|
|
186 |
DEVINIT(cpc700) |
DEVINIT(mpc40x) |
187 |
{ |
{ |
188 |
struct cpc700_data *d; |
struct mpc40x_data *d; |
189 |
char tmp[300]; |
char tmp[300]; |
190 |
int i; |
int i; |
191 |
|
|
192 |
CHECK_ALLOCATION(d = malloc(sizeof(struct cpc700_data))); |
CHECK_ALLOCATION(d = malloc(sizeof(struct mpc40x_data))); |
193 |
memset(d, 0, sizeof(struct cpc700_data)); |
memset(d, 0, sizeof(struct mpc40x_data)); |
194 |
|
|
195 |
/* Connect to the CPU's interrupt pin: */ |
/* Connect to the CPU's interrupt pin: */ |
196 |
INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq); |
INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq); |
197 |
|
|
198 |
/* Register 32 CPC700 interrupts: */ |
/* Register 32 MPC40X interrupts: */ |
199 |
for (i=0; i<32; i++) { |
for (i=0; i<32; i++) { |
200 |
struct interrupt template; |
struct interrupt template; |
201 |
char n[300]; |
char n[300]; |
202 |
snprintf(n, sizeof(n), "%s.cpc700.%i", |
snprintf(n, sizeof(n), "%s.mpc40x.%i", |
203 |
devinit->interrupt_path, i); |
devinit->interrupt_path, i); |
204 |
memset(&template, 0, sizeof(template)); |
memset(&template, 0, sizeof(template)); |
205 |
template.line = 1 << i; |
template.line = 1 << i; |
206 |
template.name = n; |
template.name = n; |
207 |
template.extra = d; |
template.extra = d; |
208 |
template.interrupt_assert = cpc700_interrupt_assert; |
template.interrupt_assert = mpc40x_interrupt_assert; |
209 |
template.interrupt_deassert = cpc700_interrupt_deassert; |
template.interrupt_deassert = mpc40x_interrupt_deassert; |
210 |
interrupt_handler_register(&template); |
interrupt_handler_register(&template); |
211 |
} |
} |
212 |
|
|
213 |
/* Register a PCI bus: */ |
/* Register a PCI bus: */ |
214 |
snprintf(tmp, sizeof(tmp), "%s.cpc700", devinit->interrupt_path); |
snprintf(tmp, sizeof(tmp), "%s.mpc40x", devinit->interrupt_path); |
215 |
d->pci_data = bus_pci_init( |
d->pci_data = bus_pci_init( |
216 |
devinit->machine, |
devinit->machine, |
217 |
tmp, /* pciirq path */ |
tmp, /* pciirq path */ |
218 |
0, /* pci device io offset */ |
0, /* pci device io offset */ |
219 |
0, /* pci device mem offset */ |
0, /* pci device mem offset */ |
220 |
CPC_PCI_IO_BASE, /* PCI portbase */ |
MPC_PCI_IO_BASE, /* PCI portbase */ |
221 |
CPC_PCI_MEM_BASE, /* PCI membase: TODO */ |
MPC_PCI_MEM_BASE, /* PCI membase: TODO */ |
222 |
tmp, /* PCI irqbase */ |
tmp, /* PCI irqbase */ |
223 |
0, /* ISA portbase: TODO */ |
0, /* ISA portbase: TODO */ |
224 |
0, /* ISA membase: TODO */ |
0, /* ISA membase: TODO */ |
225 |
tmp); /* ISA irqbase */ |
tmp); /* ISA irqbase */ |
226 |
|
|
227 |
|
#if 0 |
228 |
switch (devinit->machine->machine_type) { |
switch (devinit->machine->machine_type) { |
229 |
|
|
230 |
case MACHINE_PMPPC: |
case MACHINE_SANDPOINT: |
231 |
bus_pci_add(devinit->machine, d->pci_data, |
bus_pci_add(devinit->machine, d->pci_data, |
232 |
devinit->machine->memory, 0, 0, 0, "heuricon_pmppc"); |
devinit->machine->memory, 0, 0, 0, "sandpoint_pci"); |
233 |
break; |
break; |
234 |
|
|
235 |
default:fatal("!\n! WARNING: cpc700 for non-implemented machine" |
default:fatal("!\n! WARNING: mpc40x for non-implemented machine" |
236 |
" type\n!\n"); |
" type\n!\n"); |
237 |
exit(1); |
exit(1); |
238 |
} |
} |
239 |
|
#endif |
240 |
|
|
241 |
/* PCI configuration registers: */ |
/* PCI configuration registers: */ |
242 |
memory_device_register(devinit->machine->memory, "cpc700_pci", |
memory_device_register(devinit->machine->memory, "mpc40x_pci", |
243 |
CPC_PCICFGADR, 8, dev_cpc700_pci_access, d, DM_DEFAULT, NULL); |
MPC_PCICFGADR, 8, dev_mpc40x_pci_access, d, DM_DEFAULT, NULL); |
244 |
|
|
245 |
/* Interrupt controller: */ |
/* Interrupt controller: */ |
246 |
memory_device_register(devinit->machine->memory, "cpc700_int", |
memory_device_register(devinit->machine->memory, "mpc40x_int", |
247 |
CPC_UIC_BASE, CPC_UIC_SIZE, dev_cpc700_int_access, d, |
MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc40x_int_access, d, |
248 |
DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
249 |
|
|
250 |
/* Two serial ports: */ |
/* Two serial ports: */ |
251 |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx " |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc40x.%i addr=0x%llx " |
252 |
"name2=tty0", devinit->interrupt_path, 31 - CPC_IB_UART_0, |
"name2=tty0", devinit->interrupt_path, 31 - MPC_IB_UART_0, |
253 |
(long long)CPC_COM0); |
(long long)MPC_COM0); |
254 |
devinit->machine->main_console_handle = (size_t) |
devinit->machine->main_console_handle = (size_t) |
255 |
device_add(devinit->machine, tmp); |
device_add(devinit->machine, tmp); |
256 |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx " |
#if 0 |
257 |
"name2=tty1", devinit->interrupt_path, 31 - CPC_IB_UART_1, |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc40x.%i addr=0x%llx " |
258 |
(long long)CPC_COM1); |
"name2=tty1", devinit->interrupt_path, 31 - MPC_IB_UART_1, |
259 |
// device_add(devinit->machine, tmp); |
(long long)MPC_COM1); |
260 |
|
device_add(devinit->machine, tmp); |
261 |
|
#endif |
262 |
|
|
263 |
devinit->return_ptr = d->pci_data; |
devinit->return_ptr = d->pci_data; |
264 |
|
|