--- trunk/src/devices/dev_mpc10x.c 2007/10/11 18:56:50 56 +++ trunk/src/devices/dev_mpc10x.c 2007/10/11 18:57:32 57 @@ -82,8 +82,12 @@ int bus, dev, func, reg; struct mpc10x_data *d = extra; - if (writeflag == MEM_WRITE) + if (writeflag == MEM_WRITE) { idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); + debug("mpc10x_pci WRITE offset 0x%x: 0x%x\n", relative_addr, odata); + } + + debug("relative: %d i: 0x%x o: 0x%x data: %s len: %d\n", relative_addr,idata, odata, data, len ); switch (relative_addr) { case 0: /* Address: */ @@ -97,8 +101,19 @@ break; } - if (writeflag == MEM_READ) +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ + PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) + + debug("i: 0x%x o: 0x%x\n", idata, odata ); + if (writeflag == MEM_READ) { memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); + odata = MPC10X_BRIDGE_8245; + debug("mpc10x_pci READ offset 0x%x: 0x%x\n", relative_addr, odata); + } return 1; } @@ -182,6 +197,45 @@ return 1; } +/* + * dev_mpc10x_config_access(): + * + * Configuration + */ +DEVICE_ACCESS(mpc10x_config) +{ + uint64_t idata = 0, odata = 0; +// struct mpc10x_data *d = extra; + + if (writeflag == MEM_WRITE) { + idata = memory_readmax64(cpu, data, len); + debug("mpc10x_config WRITE offset 0x%x: 0x%x [old: 0x%x]\n", relative_addr, odata, idata); + } + + debug("relative: %d i: 0x%x o: 0x%x data: %s len: %d\n", relative_addr,idata, odata, data, len ); + + switch (relative_addr) { + case 0: + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ + PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) + + return MPC10X_BRIDGE_8245; + } + + debug("i: 0x%x o: 0x%x\n", idata, odata ); + if (writeflag == MEM_READ) { + odata = MPC10X_BRIDGE_8245; + memory_writemax64(cpu, data, len, odata); + debug("mpc10x_config READ offset 0x%x: 0x%x\n", relative_addr, odata); + } + + return 1; +} DEVINIT(mpc10x) { @@ -215,32 +269,26 @@ d->pci_data = bus_pci_init( devinit->machine, tmp, /* pciirq path */ - 0, /* pci device io offset */ - 0, /* pci device mem offset */ - MPC_PCI_IO_BASE, /* PCI portbase */ - MPC_PCI_MEM_BASE, /* PCI membase: TODO */ + 0xfc000000, /* pci device io offset */ + 0xfcc00000, /* pci device mem offset */ + 0xfec00000, /* PCI portbase */ + 0x80000000, /* PCI membase: TODO */ tmp, /* PCI irqbase */ 0, /* ISA portbase: TODO */ 0, /* ISA membase: TODO */ tmp); /* ISA irqbase */ -#if 0 - switch (devinit->machine->machine_type) { - - case MACHINE_SANDPOINT: - bus_pci_add(devinit->machine, d->pci_data, - devinit->machine->memory, 0, 0, 0, "sandpoint_pci"); - break; - - default:fatal("!\n! WARNING: mpc10x for non-implemented machine" - " type\n!\n"); - exit(1); - } -#endif + /* PCI host bridge */ + bus_pci_add(devinit->machine, d->pci_data, + devinit->machine->memory, 0, 0, 0, "mpc10x_host_bridge"); + + /* MPC10x configuration */ + memory_device_register(devinit->machine->memory, "mpc10x_config", + 0xfec00000, 8, dev_mpc10x_config_access, d, DM_DEFAULT, NULL); /* PCI configuration registers: */ memory_device_register(devinit->machine->memory, "mpc10x_pci", - MPC10X_MAPB_CNFG_DATA, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); + 0xfee00000, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); /* Interrupt controller: */ memory_device_register(devinit->machine->memory, "mpc10x_int",