202 |
* |
* |
203 |
* Configuration |
* Configuration |
204 |
*/ |
*/ |
205 |
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206 |
DEVICE_ACCESS(mpc10x_config) |
DEVICE_ACCESS(mpc10x_config) |
207 |
{ |
{ |
208 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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// struct mpc10x_data *d = extra; |
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209 |
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210 |
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debug("mpc10x_config relative: %d i: 0x%x o: 0x%x data: %s len: %d write: %d\n", relative_addr,idata, odata, data, len, writeflag ); |
211 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
212 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
213 |
debug("mpc10x_config WRITE offset 0x%x: 0x%x [old: 0x%x]\n", relative_addr, odata, idata); |
debug("[ mpc10x_config WRITE offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
214 |
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} else { |
215 |
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fatal("[ mpc10x_config: read! ]\n"); |
216 |
} |
} |
217 |
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218 |
debug("relative: %d i: 0x%x o: 0x%x data: %s len: %d\n", relative_addr,idata, odata, data, len ); |
return 1; |
219 |
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} |
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switch (relative_addr) { |
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case 0: |
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220 |
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221 |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
222 |
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
225 |
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
226 |
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
227 |
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|
228 |
return MPC10X_BRIDGE_8245; |
DEVICE_ACCESS(mpc10x_data) |
229 |
} |
{ |
230 |
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uint64_t idata = 0, odata = 0; |
231 |
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232 |
debug("i: 0x%x o: 0x%x\n", idata, odata ); |
debug("mpc10x_data: relative: %d i: 0x%x o: 0x%x data: %s len: %d write: %d\n", relative_addr,idata, odata, data, len, writeflag ); |
233 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_WRITE) { |
234 |
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idata = memory_readmax64(cpu, data, len); |
235 |
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fatal("[ mpc10x_data: write -> %x ]\n", idata); |
236 |
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} else { |
237 |
odata = MPC10X_BRIDGE_8245; |
odata = MPC10X_BRIDGE_8245; |
238 |
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debug("[ mpc10x_data: READ offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
239 |
memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len, odata); |
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debug("mpc10x_config READ offset 0x%x: 0x%x\n", relative_addr, odata); |
|
240 |
} |
} |
241 |
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242 |
return 1; |
return 1; |
243 |
} |
} |
244 |
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245 |
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246 |
DEVINIT(mpc10x) |
DEVINIT(mpc10x) |
247 |
{ |
{ |
248 |
struct mpc10x_data *d; |
struct mpc10x_data *d; |
270 |
interrupt_handler_register(&template); |
interrupt_handler_register(&template); |
271 |
} |
} |
272 |
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273 |
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#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
274 |
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#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
275 |
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276 |
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#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
277 |
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#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
278 |
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#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
279 |
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280 |
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#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
281 |
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#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
282 |
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#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
283 |
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#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
284 |
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|
285 |
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#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
286 |
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MPC10X_MAPB_PCI_MEM_START) |
287 |
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288 |
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289 |
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|
290 |
/* Register a PCI bus: */ |
/* Register a PCI bus: */ |
291 |
snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
292 |
d->pci_data = bus_pci_init( |
d->pci_data = bus_pci_init( |
293 |
devinit->machine, |
devinit->machine, |
294 |
tmp, /* pciirq path */ |
tmp, /* pciirq path */ |
295 |
0xfc000000, /* pci device io offset */ |
0x00000000, /* pci device io offset */ |
296 |
0xfcc00000, /* pci device mem offset */ |
0x00000000, /* pci device mem offset */ |
297 |
0xfec00000, /* PCI portbase */ |
0xfe000000, /* PCI portbase */ |
298 |
0x80000000, /* PCI membase: TODO */ |
0x80000000, /* PCI membase: TODO */ |
299 |
tmp, /* PCI irqbase */ |
tmp, /* PCI irqbase */ |
300 |
0, /* ISA portbase: TODO */ |
0xfe000000, /* ISA portbase: TODO */ |
301 |
0, /* ISA membase: TODO */ |
0x80000000, /* ISA membase: TODO */ |
302 |
tmp); /* ISA irqbase */ |
tmp); /* ISA irqbase */ |
303 |
|
|
304 |
/* PCI host bridge */ |
/* PCI host bridge */ |
307 |
|
|
308 |
/* MPC10x configuration */ |
/* MPC10x configuration */ |
309 |
memory_device_register(devinit->machine->memory, "mpc10x_config", |
memory_device_register(devinit->machine->memory, "mpc10x_config", |
310 |
0xfec00000, 8, dev_mpc10x_config_access, d, DM_DEFAULT, NULL); |
0xfec00000, 1, dev_mpc10x_config_access, d, DM_DEFAULT, NULL); |
311 |
|
memory_device_register(devinit->machine->memory, "mpc10x_data", |
312 |
|
0xfee00000, 8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL); |
313 |
|
|
314 |
|
#if 0 |
315 |
/* PCI configuration registers: */ |
/* PCI configuration registers: */ |
316 |
memory_device_register(devinit->machine->memory, "mpc10x_pci", |
memory_device_register(devinit->machine->memory, "mpc10x_pci", |
317 |
0xfee00000, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
0xfee00000, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
320 |
memory_device_register(devinit->machine->memory, "mpc10x_int", |
memory_device_register(devinit->machine->memory, "mpc10x_int", |
321 |
MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
322 |
DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
323 |
|
#endif |
324 |
|
|
325 |
/* Two serial ports: */ |
/* Two serial ports: */ |
326 |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |