27 |
* |
* |
28 |
* $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
* $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
29 |
* |
* |
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* COMMENT: IBM mpc10x bridge (PCI and interrupt controller) |
* COMMENT: mpc10x bridge (PCI and interrupt controller) |
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* based on dev_uninorth.c |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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46 |
#include "mpc10xreg.h" |
#if 0 |
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struct mpc10x_data { |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
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struct interrupt ppc_irq; /* Connected to the CPU */ |
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
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PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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55 |
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#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
56 |
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#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
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#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
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#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
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#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
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#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
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#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
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#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
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#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
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uint32_t sr; /* Interrupt Status register */ |
#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
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uint32_t er; /* Interrupt Enable register */ |
MPC10X_MAPB_PCI_MEM_START) |
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struct pci_data *pci_data; /* PCI bus */ |
#endif |
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}; |
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struct mpc10x_data { |
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int pciirq; |
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void mpc10x_interrupt_assert(struct interrupt *interrupt) |
struct pci_data *pci_data; |
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{ |
uint64_t cur_addr; |
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struct mpc10x_data *d = interrupt->extra; |
}; |
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d->sr |= interrupt->line; |
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if (d->sr & d->er) |
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INTERRUPT_ASSERT(d->ppc_irq); |
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} |
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void mpc10x_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct mpc10x_data *d = interrupt->extra; |
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d->sr &= ~interrupt->line; |
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if (!(d->sr & d->er)) |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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/* |
DEVICE_ACCESS(mpc10x_addr) |
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* dev_mpc10x_pci_access(): |
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* |
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* Passes PCI indirect addr and data accesses onto bus_pci. |
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*/ |
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DEVICE_ACCESS(mpc10x_pci) |
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{ |
{ |
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uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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struct mpc10x_data *d = extra; |
struct mpc10x_data *d = extra; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
uint64_t idata = memory_readmax64(cpu, data, len |
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| MEM_PCI_LITTLE_ENDIAN); |
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int bus, dev, func, reg; |
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d->cur_addr = idata; |
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if (idata == 0) |
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return 0; |
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/* Decompose the Uni-North tag: */ |
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if (idata & 1) { |
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idata &= ~1; |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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} else { |
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bus = 0; |
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for (dev=11; dev<32; dev++) |
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if (idata & (1 << dev)) |
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break; |
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if (dev == 32) |
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fatal("[ dev_mpc10x_addr_access: no dev? " |
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"idata=0x%08x ]\n", (int)idata); |
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switch (relative_addr) { |
func = (idata >> 8) & 7; |
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case 0: /* Address: */ |
reg = idata & 0xff; |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
} |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
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case 4: /* Data: */ |
bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
} else { |
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&odata : &idata, len, writeflag); |
/* TODO: is returning the current address like this |
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break; |
the correct behaviour? */ |
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memory_writemax64(cpu, data, len | MEM_PCI_LITTLE_ENDIAN, |
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d->cur_addr); |
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} |
} |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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return 1; |
return 1; |
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} |
} |
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/* |
DEVICE_ACCESS(mpc10x_data) |
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* dev_mpc10x_int_access(): |
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* |
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* The interrupt controller. |
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*/ |
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DEVICE_ACCESS(mpc10x_int) |
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{ |
{ |
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struct mpc10x_data *d = extra; |
struct mpc10x_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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switch (relative_addr) { |
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case MPC_UIC_SR: |
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/* Status register (cleared by writing ones): */ |
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if (writeflag == MEM_READ) { |
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odata = d->sr; |
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} else { |
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d->sr &= ~idata; |
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if (!(d->sr & d->er)) |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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break; |
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case MPC_UIC_SRS: |
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/* Status register set: */ |
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if (writeflag == MEM_READ) { |
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fatal("[ mpc10x_int: read from MPC_UIC_SRS? ]\n"); |
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odata = d->sr; |
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} else { |
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d->sr = idata; |
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if (d->sr & d->er) |
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INTERRUPT_ASSERT(d->ppc_irq); |
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else |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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break; |
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case MPC_UIC_ER: |
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/* Enable register: */ |
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if (writeflag == MEM_READ) { |
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odata = d->er; |
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} else { |
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d->er = idata; |
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if (d->sr & d->er) |
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INTERRUPT_ASSERT(d->ppc_irq); |
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else |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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break; |
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case MPC_UIC_MSR: |
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/* Masked status: */ |
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if (writeflag == MEM_READ) { |
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odata = d->sr & d->er; |
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} else { |
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fatal("[ mpc10x_int: write to MPC_UIC_MSR? ]\n"); |
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} |
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break; |
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default:if (writeflag == MEM_WRITE) { |
bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? &odata : |
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fatal("[ mpc10x_int: unimplemented write to " |
&idata, len, writeflag); |
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"offset 0x%x: data=0x%x ]\n", (int) |
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relative_addr, (int)idata); |
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} else { |
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fatal("[ mpc10x_int: unimplemented read from " |
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"offset 0x%x ]\n", (int)relative_addr); |
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} |
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} |
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if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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return 1; |
return 1; |
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} |
} |
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DEVINIT(mpc10x) |
struct pci_data *dev_mpc10x_init(struct machine *machine, struct memory *mem, |
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uint64_t addr, int isa_irqbase, int pciirq) |
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{ |
{ |
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struct mpc10x_data *d; |
struct mpc10x_data *d; |
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char tmp[300]; |
// char tmp[100]; |
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int i; |
uint64_t pci_io_offset, pci_mem_offset; |
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uint64_t isa_portbase = 0, isa_membase = 0; |
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uint64_t pci_portbase = 0, pci_membase = 0; |
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149 |
CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data))); |
CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data))); |
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memset(d, 0, sizeof(struct mpc10x_data)); |
memset(d, 0, sizeof(struct mpc10x_data)); |
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/* Connect to the CPU's interrupt pin: */ |
d->pciirq = pciirq; |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq); |
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/* Register 32 mpc10x interrupts: */ |
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for (i=0; i<32; i++) { |
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struct interrupt template; |
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char n[300]; |
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snprintf(n, sizeof(n), "%s.mpc10x.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = mpc10x_interrupt_assert; |
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template.interrupt_deassert = mpc10x_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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/* Register a PCI bus: */ |
pci_io_offset = 0x00000000ULL; |
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snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
pci_mem_offset = 0x00000000ULL; |
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d->pci_data = bus_pci_init( |
pci_portbase = 0xfebffe00ULL; |
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devinit->machine, |
pci_membase = 0x80000000ULL; |
158 |
tmp, /* pciirq path */ |
isa_portbase = 0xfe000000ULL; |
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0, /* pci device io offset */ |
isa_membase = 0x80000000ULL; |
160 |
0, /* pci device mem offset */ |
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161 |
MPC_PCI_IO_BASE, /* PCI portbase */ |
/* Create a PCI bus: */ |
162 |
MPC_PCI_MEM_BASE, /* PCI membase: TODO */ |
d->pci_data = bus_pci_init(machine, "ZZZ_irq_stuff", |
163 |
tmp, /* PCI irqbase */ |
pci_io_offset, pci_mem_offset, |
164 |
0, /* ISA portbase: TODO */ |
pci_portbase, pci_membase, "XXX_pci_irqbase", |
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0, /* ISA membase: TODO */ |
isa_portbase, isa_membase, "YYY_isa_irqbase"); |
166 |
tmp); /* ISA irqbase */ |
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/* Add the PCI glue for the controller itself: */ |
168 |
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bus_pci_add(machine, d->pci_data, mem, 0, 0x1f, 0, "mpc10x"); |
169 |
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170 |
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/* ADDR and DATA configuration ports: */ |
171 |
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memory_device_register(mem, "mpc10x_pci_addr", addr + 0xc00000, |
172 |
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4, dev_mpc10x_addr_access, d, DM_DEFAULT, NULL); |
173 |
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memory_device_register(mem, "mpc10x_pci_data", addr + 0xe00000, |
174 |
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8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL); |
175 |
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176 |
#if 0 |
return d->pci_data; |
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switch (devinit->machine->machine_type) { |
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case MACHINE_SANDPOINT: |
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bus_pci_add(devinit->machine, d->pci_data, |
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devinit->machine->memory, 0, 0, 0, "sandpoint_pci"); |
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break; |
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default:fatal("!\n! WARNING: mpc10x for non-implemented machine" |
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" type\n!\n"); |
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exit(1); |
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} |
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#endif |
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/* PCI configuration registers: */ |
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memory_device_register(devinit->machine->memory, "mpc10x_pci", |
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MPC10X_MAPB_CNFG_DATA, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
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/* Interrupt controller: */ |
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memory_device_register(devinit->machine->memory, "mpc10x_int", |
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MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
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DM_DEFAULT, NULL); |
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/* Two serial ports: */ |
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snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
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"name2=tty0", devinit->interrupt_path, 31 - MPC_IB_UART_0, |
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(long long)MPC_COM0); |
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devinit->machine->main_console_handle = (size_t) |
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device_add(devinit->machine, tmp); |
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#if 0 |
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snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
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"name2=tty1", devinit->interrupt_path, 31 - MPC_IB_UART_1, |
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(long long)MPC_COM1); |
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device_add(devinit->machine, tmp); |
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#endif |
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devinit->return_ptr = d->pci_data; |
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return 1; |
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177 |
} |
} |
178 |
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