82 |
int bus, dev, func, reg; |
int bus, dev, func, reg; |
83 |
struct mpc10x_data *d = extra; |
struct mpc10x_data *d = extra; |
84 |
|
|
85 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
86 |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
87 |
|
debug("mpc10x_pci WRITE offset 0x%x: 0x%x\n", relative_addr, odata); |
88 |
|
} |
89 |
|
|
90 |
|
debug("relative: %d i: 0x%x o: 0x%x data: %s len: %d\n", relative_addr,idata, odata, data, len ); |
91 |
|
|
92 |
switch (relative_addr) { |
switch (relative_addr) { |
93 |
case 0: /* Address: */ |
case 0: /* Address: */ |
101 |
break; |
break; |
102 |
} |
} |
103 |
|
|
104 |
if (writeflag == MEM_READ) |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
105 |
|
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
106 |
|
PCI_VENDOR_ID_MOTOROLA) |
107 |
|
#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
108 |
|
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
109 |
|
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
110 |
|
|
111 |
|
debug("i: 0x%x o: 0x%x\n", idata, odata ); |
112 |
|
if (writeflag == MEM_READ) { |
113 |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
114 |
|
odata = MPC10X_BRIDGE_8245; |
115 |
|
debug("mpc10x_pci READ offset 0x%x: 0x%x\n", relative_addr, odata); |
116 |
|
} |
117 |
|
|
118 |
return 1; |
return 1; |
119 |
} |
} |
197 |
return 1; |
return 1; |
198 |
} |
} |
199 |
|
|
200 |
|
/* |
201 |
|
* dev_mpc10x_config_access(): |
202 |
|
* |
203 |
|
* Configuration |
204 |
|
*/ |
205 |
|
|
206 |
|
DEVICE_ACCESS(mpc10x_config) |
207 |
|
{ |
208 |
|
uint64_t idata = 0, odata = 0; |
209 |
|
|
210 |
|
debug("mpc10x_config relative: %d i: 0x%x o: 0x%x data: %x len: %x write: %x w: %x r: %x\n", relative_addr,idata, odata, data, len, writeflag, MEM_WRITE, MEM_READ ); |
211 |
|
if (writeflag == MEM_WRITE) { |
212 |
|
idata = memory_readmax64(cpu, data, len); |
213 |
|
debug("[ mpc10x_config WRITE offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
214 |
|
} |
215 |
|
if (writeflag == MEM_READ) { |
216 |
|
fatal("[ mpc10x_config: read! ]\n"); |
217 |
|
} |
218 |
|
|
219 |
|
return 1; |
220 |
|
} |
221 |
|
|
222 |
|
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
223 |
|
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
224 |
|
PCI_VENDOR_ID_MOTOROLA) |
225 |
|
#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
226 |
|
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
227 |
|
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
228 |
|
|
229 |
|
DEVICE_ACCESS(mpc10x_data) |
230 |
|
{ |
231 |
|
uint64_t idata = 0, odata = 0; |
232 |
|
|
233 |
|
debug("mpc10x_data: relative: %d i: 0x%x o: 0x%x data: %s len: %d write: %d\n", relative_addr,idata, odata, data, len, writeflag ); |
234 |
|
if (writeflag == MEM_WRITE) { |
235 |
|
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
236 |
|
fatal("[ mpc10x_data: write -> %x ]\n", (int)idata); |
237 |
|
} |
238 |
|
if (writeflag == MEM_READ) { |
239 |
|
odata = MPC10X_BRIDGE_8245; |
240 |
|
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
241 |
|
debug("odata = %x\n", (int)odata); |
242 |
|
debug("[ mpc10x_data: READ offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
243 |
|
} |
244 |
|
|
245 |
|
return 1; |
246 |
|
} |
247 |
|
|
248 |
|
|
249 |
DEVINIT(mpc10x) |
DEVINIT(mpc10x) |
250 |
{ |
{ |
273 |
interrupt_handler_register(&template); |
interrupt_handler_register(&template); |
274 |
} |
} |
275 |
|
|
276 |
|
#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
277 |
|
#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
278 |
|
|
279 |
|
#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
280 |
|
#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
281 |
|
#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
282 |
|
|
283 |
|
#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
284 |
|
#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
285 |
|
#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
286 |
|
#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
287 |
|
|
288 |
|
#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
289 |
|
MPC10X_MAPB_PCI_MEM_START) |
290 |
|
|
291 |
|
|
292 |
|
|
293 |
/* Register a PCI bus: */ |
/* Register a PCI bus: */ |
294 |
snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
295 |
d->pci_data = bus_pci_init( |
d->pci_data = bus_pci_init( |
296 |
devinit->machine, |
devinit->machine, |
297 |
tmp, /* pciirq path */ |
tmp, /* pciirq path */ |
298 |
0, /* pci device io offset */ |
0x00000000, /* pci device io offset */ |
299 |
0, /* pci device mem offset */ |
0x00000000, /* pci device mem offset */ |
300 |
MPC_PCI_IO_BASE, /* PCI portbase */ |
0xfe000000, /* PCI portbase */ |
301 |
MPC_PCI_MEM_BASE, /* PCI membase: TODO */ |
0x80000000, /* PCI membase: TODO */ |
302 |
tmp, /* PCI irqbase */ |
tmp, /* PCI irqbase */ |
303 |
0, /* ISA portbase: TODO */ |
0xfe000000, /* ISA portbase: TODO */ |
304 |
0, /* ISA membase: TODO */ |
0x80000000, /* ISA membase: TODO */ |
305 |
tmp); /* ISA irqbase */ |
tmp); /* ISA irqbase */ |
306 |
|
|
307 |
#if 0 |
/* PCI host bridge */ |
308 |
switch (devinit->machine->machine_type) { |
bus_pci_add(devinit->machine, d->pci_data, |
309 |
|
devinit->machine->memory, 0, 0, 0, "mpc10x_host_bridge"); |
310 |
case MACHINE_SANDPOINT: |
|
311 |
bus_pci_add(devinit->machine, d->pci_data, |
/* MPC10x configuration */ |
312 |
devinit->machine->memory, 0, 0, 0, "sandpoint_pci"); |
memory_device_register(devinit->machine->memory, "mpc10x_config", |
313 |
break; |
0xfec00000, 1, dev_mpc10x_config_access, d, DM_DEFAULT, NULL); |
314 |
|
memory_device_register(devinit->machine->memory, "mpc10x_data", |
315 |
default:fatal("!\n! WARNING: mpc10x for non-implemented machine" |
0xfee00000, 8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL); |
|
" type\n!\n"); |
|
|
exit(1); |
|
|
} |
|
|
#endif |
|
316 |
|
|
317 |
|
#if 0 |
318 |
/* PCI configuration registers: */ |
/* PCI configuration registers: */ |
319 |
memory_device_register(devinit->machine->memory, "mpc10x_pci", |
memory_device_register(devinit->machine->memory, "mpc10x_pci", |
320 |
MPC10X_MAPB_CNFG_DATA, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
0xfee00000, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
321 |
|
|
322 |
/* Interrupt controller: */ |
/* Interrupt controller: */ |
323 |
memory_device_register(devinit->machine->memory, "mpc10x_int", |
memory_device_register(devinit->machine->memory, "mpc10x_int", |
324 |
MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
325 |
DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
326 |
|
#endif |
327 |
|
|
328 |
/* Two serial ports: */ |
/* Two serial ports: */ |
329 |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |