25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_cpc700.c,v 1.10 2007/01/29 19:03:16 debug Exp $ |
* $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
29 |
* |
* |
30 |
* IBM CPC700 bridge; PCI and interrupt controller. |
* COMMENT: IBM mpc10x bridge (PCI and interrupt controller) |
31 |
*/ |
*/ |
32 |
|
|
33 |
#include <stdio.h> |
#include <stdio.h> |
37 |
#include "bus_pci.h" |
#include "bus_pci.h" |
38 |
#include "cpu.h" |
#include "cpu.h" |
39 |
#include "device.h" |
#include "device.h" |
40 |
|
#include "interrupt.h" |
41 |
#include "machine.h" |
#include "machine.h" |
42 |
#include "memory.h" |
#include "memory.h" |
43 |
#include "misc.h" |
#include "misc.h" |
44 |
|
|
45 |
#include "cpc700reg.h" |
#include "mpc10xreg.h" |
46 |
|
|
47 |
|
|
48 |
struct cpc700_data { |
struct mpc10x_data { |
49 |
struct interrupt ppc_irq; /* Connected to the CPU */ |
struct interrupt ppc_irq; /* Connected to the CPU */ |
50 |
|
|
51 |
uint32_t sr; /* Interrupt Status register */ |
uint32_t sr; /* Interrupt Status register */ |
55 |
}; |
}; |
56 |
|
|
57 |
|
|
58 |
void cpc700_interrupt_assert(struct interrupt *interrupt) |
void mpc10x_interrupt_assert(struct interrupt *interrupt) |
59 |
{ |
{ |
60 |
struct cpc700_data *d = interrupt->extra; |
struct mpc10x_data *d = interrupt->extra; |
61 |
d->sr |= (1 << interrupt->line); |
d->sr |= interrupt->line; |
62 |
if (d->sr & d->er) |
if (d->sr & d->er) |
63 |
INTERRUPT_ASSERT(d->ppc_irq); |
INTERRUPT_ASSERT(d->ppc_irq); |
64 |
} |
} |
65 |
void cpc700_interrupt_deassert(struct interrupt *interrupt) |
void mpc10x_interrupt_deassert(struct interrupt *interrupt) |
66 |
{ |
{ |
67 |
struct cpc700_data *d = interrupt->extra; |
struct mpc10x_data *d = interrupt->extra; |
68 |
d->sr &= ~(1 << interrupt->line); |
d->sr &= ~interrupt->line; |
69 |
if (!(d->sr & d->er)) |
if (!(d->sr & d->er)) |
70 |
INTERRUPT_DEASSERT(d->ppc_irq); |
INTERRUPT_DEASSERT(d->ppc_irq); |
71 |
} |
} |
72 |
|
|
73 |
|
|
74 |
/* |
/* |
75 |
* dev_cpc700_pci_access(): |
* dev_mpc10x_pci_access(): |
76 |
* |
* |
77 |
* Passes PCI indirect addr and data accesses onto bus_pci. |
* Passes PCI indirect addr and data accesses onto bus_pci. |
78 |
*/ |
*/ |
79 |
DEVICE_ACCESS(cpc700_pci) |
DEVICE_ACCESS(mpc10x_pci) |
80 |
{ |
{ |
81 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
82 |
int bus, dev, func, reg; |
int bus, dev, func, reg; |
83 |
struct cpc700_data *d = extra; |
struct mpc10x_data *d = extra; |
84 |
|
|
85 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) { |
86 |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
87 |
|
debug("mpc10x_pci WRITE offset 0x%x: 0x%x\n", relative_addr, odata); |
88 |
|
} |
89 |
|
|
90 |
|
debug("relative: %d i: 0x%x o: 0x%x data: %s len: %d\n", relative_addr,idata, odata, data, len ); |
91 |
|
|
92 |
switch (relative_addr) { |
switch (relative_addr) { |
93 |
case 0: /* Address: */ |
case 0: /* Address: */ |
101 |
break; |
break; |
102 |
} |
} |
103 |
|
|
104 |
if (writeflag == MEM_READ) |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
105 |
|
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
106 |
|
PCI_VENDOR_ID_MOTOROLA) |
107 |
|
#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
108 |
|
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
109 |
|
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
110 |
|
|
111 |
|
debug("i: 0x%x o: 0x%x\n", idata, odata ); |
112 |
|
if (writeflag == MEM_READ) { |
113 |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
114 |
|
odata = MPC10X_BRIDGE_8245; |
115 |
|
debug("mpc10x_pci READ offset 0x%x: 0x%x\n", relative_addr, odata); |
116 |
|
} |
117 |
|
|
118 |
return 1; |
return 1; |
119 |
} |
} |
120 |
|
|
121 |
|
|
122 |
/* |
/* |
123 |
* dev_cpc700_int_access(): |
* dev_mpc10x_int_access(): |
124 |
* |
* |
125 |
* The interrupt controller. |
* The interrupt controller. |
126 |
*/ |
*/ |
127 |
DEVICE_ACCESS(cpc700_int) |
DEVICE_ACCESS(mpc10x_int) |
128 |
{ |
{ |
129 |
struct cpc700_data *d = extra; |
struct mpc10x_data *d = extra; |
130 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
131 |
|
|
132 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
134 |
|
|
135 |
switch (relative_addr) { |
switch (relative_addr) { |
136 |
|
|
137 |
case CPC_UIC_SR: |
case MPC_UIC_SR: |
138 |
/* Status register (cleared by writing ones): */ |
/* Status register (cleared by writing ones): */ |
139 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
140 |
odata = d->sr; |
odata = d->sr; |
145 |
} |
} |
146 |
break; |
break; |
147 |
|
|
148 |
case CPC_UIC_SRS: |
case MPC_UIC_SRS: |
149 |
/* Status register set: */ |
/* Status register set: */ |
150 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
151 |
fatal("[ cpc700_int: read from CPC_UIC_SRS? ]\n"); |
fatal("[ mpc10x_int: read from MPC_UIC_SRS? ]\n"); |
152 |
odata = d->sr; |
odata = d->sr; |
153 |
} else { |
} else { |
154 |
d->sr = idata; |
d->sr = idata; |
159 |
} |
} |
160 |
break; |
break; |
161 |
|
|
162 |
case CPC_UIC_ER: |
case MPC_UIC_ER: |
163 |
/* Enable register: */ |
/* Enable register: */ |
164 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
165 |
odata = d->er; |
odata = d->er; |
172 |
} |
} |
173 |
break; |
break; |
174 |
|
|
175 |
case CPC_UIC_MSR: |
case MPC_UIC_MSR: |
176 |
/* Masked status: */ |
/* Masked status: */ |
177 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
178 |
odata = d->sr & d->er; |
odata = d->sr & d->er; |
179 |
} else { |
} else { |
180 |
fatal("[ cpc700_int: write to CPC_UIC_MSR? ]\n"); |
fatal("[ mpc10x_int: write to MPC_UIC_MSR? ]\n"); |
181 |
} |
} |
182 |
break; |
break; |
183 |
|
|
184 |
default:if (writeflag == MEM_WRITE) { |
default:if (writeflag == MEM_WRITE) { |
185 |
fatal("[ cpc700_int: unimplemented write to " |
fatal("[ mpc10x_int: unimplemented write to " |
186 |
"offset 0x%x: data=0x%x ]\n", (int) |
"offset 0x%x: data=0x%x ]\n", (int) |
187 |
relative_addr, (int)idata); |
relative_addr, (int)idata); |
188 |
} else { |
} else { |
189 |
fatal("[ cpc700_int: unimplemented read from " |
fatal("[ mpc10x_int: unimplemented read from " |
190 |
"offset 0x%x ]\n", (int)relative_addr); |
"offset 0x%x ]\n", (int)relative_addr); |
191 |
} |
} |
192 |
} |
} |
197 |
return 1; |
return 1; |
198 |
} |
} |
199 |
|
|
200 |
|
/* |
201 |
|
* dev_mpc10x_config_access(): |
202 |
|
* |
203 |
|
* Configuration |
204 |
|
*/ |
205 |
|
|
206 |
DEVINIT(cpc700) |
DEVICE_ACCESS(mpc10x_config) |
207 |
{ |
{ |
208 |
struct cpc700_data *d; |
uint64_t idata = 0, odata = 0; |
209 |
|
|
210 |
|
debug("mpc10x_config relative: %d i: 0x%x o: 0x%x data: %s len: %d write: %d\n", relative_addr,idata, odata, data, len, writeflag ); |
211 |
|
if (writeflag == MEM_WRITE) { |
212 |
|
idata = memory_readmax64(cpu, data, len); |
213 |
|
debug("[ mpc10x_config WRITE offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
214 |
|
} else { |
215 |
|
fatal("[ mpc10x_config: read! ]\n"); |
216 |
|
} |
217 |
|
|
218 |
|
return 1; |
219 |
|
} |
220 |
|
|
221 |
|
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
222 |
|
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
223 |
|
PCI_VENDOR_ID_MOTOROLA) |
224 |
|
#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
225 |
|
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
226 |
|
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
227 |
|
|
228 |
|
DEVICE_ACCESS(mpc10x_data) |
229 |
|
{ |
230 |
|
uint64_t idata = 0, odata = 0; |
231 |
|
|
232 |
|
debug("mpc10x_data: relative: %d i: 0x%x o: 0x%x data: %s len: %d write: %d\n", relative_addr,idata, odata, data, len, writeflag ); |
233 |
|
if (writeflag == MEM_WRITE) { |
234 |
|
idata = memory_readmax64(cpu, data, len); |
235 |
|
fatal("[ mpc10x_data: write -> %x ]\n", idata); |
236 |
|
} else { |
237 |
|
odata = MPC10X_BRIDGE_8245; |
238 |
|
debug("[ mpc10x_data: READ offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
239 |
|
memory_writemax64(cpu, data, len, odata); |
240 |
|
} |
241 |
|
|
242 |
|
return 1; |
243 |
|
} |
244 |
|
|
245 |
|
|
246 |
|
DEVINIT(mpc10x) |
247 |
|
{ |
248 |
|
struct mpc10x_data *d; |
249 |
char tmp[300]; |
char tmp[300]; |
250 |
int i; |
int i; |
251 |
|
|
252 |
d = malloc(sizeof(struct cpc700_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data))); |
253 |
if (d == NULL) { |
memset(d, 0, sizeof(struct mpc10x_data)); |
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
|
memset(d, 0, sizeof(struct cpc700_data)); |
|
254 |
|
|
255 |
/* Connect to the CPU's interrupt pin: */ |
/* Connect to the CPU's interrupt pin: */ |
256 |
INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq); |
INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq); |
257 |
|
|
258 |
/* Register 32 CPC700 interrupts: */ |
/* Register 32 mpc10x interrupts: */ |
259 |
for (i=0; i<32; i++) { |
for (i=0; i<32; i++) { |
260 |
struct interrupt template; |
struct interrupt template; |
261 |
char n[300]; |
char n[300]; |
262 |
snprintf(n, sizeof(n), "%s.cpc700.%i", |
snprintf(n, sizeof(n), "%s.mpc10x.%i", |
263 |
devinit->interrupt_path, i); |
devinit->interrupt_path, i); |
264 |
memset(&template, 0, sizeof(template)); |
memset(&template, 0, sizeof(template)); |
265 |
template.line = i; |
template.line = 1 << i; |
266 |
template.name = n; |
template.name = n; |
267 |
template.extra = d; |
template.extra = d; |
268 |
template.interrupt_assert = cpc700_interrupt_assert; |
template.interrupt_assert = mpc10x_interrupt_assert; |
269 |
template.interrupt_deassert = cpc700_interrupt_deassert; |
template.interrupt_deassert = mpc10x_interrupt_deassert; |
270 |
interrupt_handler_register(&template); |
interrupt_handler_register(&template); |
271 |
} |
} |
272 |
|
|
273 |
|
#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
274 |
|
#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
275 |
|
|
276 |
|
#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
277 |
|
#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
278 |
|
#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
279 |
|
|
280 |
|
#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
281 |
|
#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
282 |
|
#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
283 |
|
#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
284 |
|
|
285 |
|
#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
286 |
|
MPC10X_MAPB_PCI_MEM_START) |
287 |
|
|
288 |
|
|
289 |
|
|
290 |
/* Register a PCI bus: */ |
/* Register a PCI bus: */ |
291 |
snprintf(tmp, sizeof(tmp), "%s.cpc700", devinit->interrupt_path); |
snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
292 |
d->pci_data = bus_pci_init( |
d->pci_data = bus_pci_init( |
293 |
devinit->machine, |
devinit->machine, |
294 |
tmp, /* pciirq path */ |
tmp, /* pciirq path */ |
295 |
0, /* pci device io offset */ |
0x00000000, /* pci device io offset */ |
296 |
0, /* pci device mem offset */ |
0x00000000, /* pci device mem offset */ |
297 |
CPC_PCI_IO_BASE, /* PCI portbase */ |
0xfe000000, /* PCI portbase */ |
298 |
CPC_PCI_MEM_BASE, /* PCI membase: TODO */ |
0x80000000, /* PCI membase: TODO */ |
299 |
tmp, /* PCI irqbase */ |
tmp, /* PCI irqbase */ |
300 |
0, /* ISA portbase: TODO */ |
0xfe000000, /* ISA portbase: TODO */ |
301 |
0, /* ISA membase: TODO */ |
0x80000000, /* ISA membase: TODO */ |
302 |
tmp); /* ISA irqbase */ |
tmp); /* ISA irqbase */ |
303 |
|
|
304 |
switch (devinit->machine->machine_type) { |
/* PCI host bridge */ |
305 |
|
bus_pci_add(devinit->machine, d->pci_data, |
306 |
case MACHINE_PMPPC: |
devinit->machine->memory, 0, 0, 0, "mpc10x_host_bridge"); |
307 |
bus_pci_add(devinit->machine, d->pci_data, |
|
308 |
devinit->machine->memory, 0, 0, 0, "heuricon_pmppc"); |
/* MPC10x configuration */ |
309 |
break; |
memory_device_register(devinit->machine->memory, "mpc10x_config", |
310 |
|
0xfec00000, 1, dev_mpc10x_config_access, d, DM_DEFAULT, NULL); |
311 |
default:fatal("!\n! WARNING: cpc700 for non-implemented machine" |
memory_device_register(devinit->machine->memory, "mpc10x_data", |
312 |
" type\n!\n"); |
0xfee00000, 8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL); |
|
exit(1); |
|
|
} |
|
313 |
|
|
314 |
|
#if 0 |
315 |
/* PCI configuration registers: */ |
/* PCI configuration registers: */ |
316 |
memory_device_register(devinit->machine->memory, "cpc700_pci", |
memory_device_register(devinit->machine->memory, "mpc10x_pci", |
317 |
CPC_PCICFGADR, 8, dev_cpc700_pci_access, d, DM_DEFAULT, NULL); |
0xfee00000, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
318 |
|
|
319 |
/* Interrupt controller: */ |
/* Interrupt controller: */ |
320 |
memory_device_register(devinit->machine->memory, "cpc700_int", |
memory_device_register(devinit->machine->memory, "mpc10x_int", |
321 |
CPC_UIC_BASE, CPC_UIC_SIZE, dev_cpc700_int_access, d, |
MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
322 |
DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
323 |
|
#endif |
324 |
|
|
325 |
/* Two serial ports: */ |
/* Two serial ports: */ |
326 |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx " |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
327 |
"name2=tty0", devinit->interrupt_path, 31 - CPC_IB_UART_0, |
"name2=tty0", devinit->interrupt_path, 31 - MPC_IB_UART_0, |
328 |
(long long)CPC_COM0); |
(long long)MPC_COM0); |
329 |
devinit->machine->main_console_handle = (size_t) |
devinit->machine->main_console_handle = (size_t) |
330 |
device_add(devinit->machine, tmp); |
device_add(devinit->machine, tmp); |
331 |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx " |
#if 0 |
332 |
"name2=tty1", devinit->interrupt_path, 31 - CPC_IB_UART_1, |
snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
333 |
(long long)CPC_COM1); |
"name2=tty1", devinit->interrupt_path, 31 - MPC_IB_UART_1, |
334 |
|
(long long)MPC_COM1); |
335 |
device_add(devinit->machine, tmp); |
device_add(devinit->machine, tmp); |
336 |
|
#endif |
337 |
|
|
338 |
devinit->return_ptr = d->pci_data; |
devinit->return_ptr = d->pci_data; |
339 |
|
|