src/devices/dev_mpc10x.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $
 *
 *  COMMENT: mpc10x bridge (PCI and interrupt controller)
 *  based on dev_uninorth.c
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cpu.h"
#include "device.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#if 0

#define PCI_VENDOR_ID_MOTOROLA          0x1057
#define MPC10X_BRIDGE_106       ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
                                  PCI_VENDOR_ID_MOTOROLA)
#define MPC10X_BRIDGE_8240      ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define MPC10X_BRIDGE_107       ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define MPC10X_BRIDGE_8245      ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)

#define MPC10X_MAPB_CNFG_ADDR           0xfec00000
#define MPC10X_MAPB_CNFG_DATA           0xfee00000

#define MPC10X_MAPB_ISA_IO_BASE         0xfe000000
#define MPC10X_MAPB_ISA_MEM_BASE        0x80000000
#define MPC10X_MAPB_DRAM_OFFSET         0x00000000

#define MPC10X_MAPB_PCI_IO_START        0x00000000
#define MPC10X_MAPB_PCI_IO_END         (0x00c00000 - 1)
#define MPC10X_MAPB_PCI_MEM_START       0x80000000
#define MPC10X_MAPB_PCI_MEM_END        (0xc0000000 - 1)

#define MPC10X_MAPB_PCI_MEM_OFFSET      (MPC10X_MAPB_ISA_MEM_BASE -     \
                                         MPC10X_MAPB_PCI_MEM_START)

#endif

struct mpc10x_data {
        int             pciirq;

        struct pci_data *pci_data;
        uint64_t        cur_addr;
};


DEVICE_ACCESS(mpc10x_addr)
{
        struct mpc10x_data *d = extra;

        if (writeflag == MEM_WRITE) {
                uint64_t idata = memory_readmax64(cpu, data, len
                    | MEM_PCI_LITTLE_ENDIAN);
                int bus, dev, func, reg;

                d->cur_addr = idata;
                if (idata == 0)
                        return 0;

                /*  Decompose the Uni-North tag:  */
                if (idata & 1) {
                        idata &= ~1;
                        bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
                } else {
                        bus = 0;
                        for (dev=11; dev<32; dev++)
                                if (idata & (1 << dev))
                                        break;
                        if (dev == 32)
                                fatal("[ dev_mpc10x_addr_access: no dev? "
                                    "idata=0x%08x ]\n", (int)idata);

                        func = (idata >> 8) & 7;
                        reg = idata & 0xff;
                }

                bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
        } else {
                /*  TODO: is returning the current address like this
                    the correct behaviour?  */
                memory_writemax64(cpu, data, len | MEM_PCI_LITTLE_ENDIAN,
                    d->cur_addr);
        }

        return 1;
}


DEVICE_ACCESS(mpc10x_data)
{
        struct mpc10x_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);

        bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? &odata :
            &idata, len, writeflag);

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);

        return 1;
}


struct pci_data *dev_mpc10x_init(struct machine *machine, struct memory *mem,
        uint64_t addr, int isa_irqbase, int pciirq)
{
        struct mpc10x_data *d;
//      char tmp[100];
        uint64_t pci_io_offset, pci_mem_offset;
        uint64_t isa_portbase = 0, isa_membase = 0;
        uint64_t pci_portbase = 0, pci_membase = 0;

        CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data)));
        memset(d, 0, sizeof(struct mpc10x_data));

        d->pciirq = pciirq;

        pci_io_offset  = 0x00000000ULL;
        pci_mem_offset = 0x00000000ULL;
        pci_portbase   = 0xd0000000ULL;
        pci_membase    = 0xd1000000ULL;
        isa_portbase   = 0xd2000000ULL;
        isa_membase    = 0xd3000000ULL;

        /*  Create a PCI bus:  */
        d->pci_data = bus_pci_init(machine, "ZZZ_irq_stuff",
            pci_io_offset, pci_mem_offset,
            pci_portbase, pci_membase, "XXX_pci_irqbase",
            isa_portbase, isa_membase, "YYY_isa_irqbase");

        /*  Add the PCI glue for the controller itself:  */
        bus_pci_add(machine, d->pci_data, mem, 0, 0x1f, 0, "mpc10x");

        /*  ADDR and DATA configuration ports:  */
        memory_device_register(mem, "mpc10x_pci_addr", addr + 0xc00000,
            4, dev_mpc10x_addr_access, d, DM_DEFAULT, NULL);
        memory_device_register(mem, "mpc10x_pci_data", addr + 0xe00000,
            8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL);

        return d->pci_data;
}

1	dpavlin	20	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	20	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	53	* $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $
29	dpavlin	42	*
30	dpavlin	61	* COMMENT: mpc10x bridge (PCI and interrupt controller)
31			* based on dev_uninorth.c
32	dpavlin	20	*/
33
34			#include <stdio.h>
35			#include <stdlib.h>
36			#include <string.h>
37
38			#include "bus_pci.h"
39			#include "cpu.h"
40			#include "device.h"
41	dpavlin	42	#include "interrupt.h"
42	dpavlin	20	#include "machine.h"
43			#include "memory.h"
44			#include "misc.h"
45
46	dpavlin	61	#if 0
47	dpavlin	20
48	dpavlin	57	#define PCI_VENDOR_ID_MOTOROLA 0x1057
49			#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) \| \
50			PCI_VENDOR_ID_MOTOROLA)
51			#define MPC10X_BRIDGE_8240 ((0x0003 << 16) \| PCI_VENDOR_ID_MOTOROLA)
52			#define MPC10X_BRIDGE_107 ((0x0004 << 16) \| PCI_VENDOR_ID_MOTOROLA)
53			#define MPC10X_BRIDGE_8245 ((0x0006 << 16) \| PCI_VENDOR_ID_MOTOROLA)
54
55	dpavlin	61	#define MPC10X_MAPB_CNFG_ADDR 0xfec00000
56			#define MPC10X_MAPB_CNFG_DATA 0xfee00000
57	dpavlin	20
58	dpavlin	61	#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000
59			#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000
60			#define MPC10X_MAPB_DRAM_OFFSET 0x00000000
61	dpavlin	20
62	dpavlin	61	#define MPC10X_MAPB_PCI_IO_START 0x00000000
63			#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1)
64			#define MPC10X_MAPB_PCI_MEM_START 0x80000000
65			#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1)
66	dpavlin	20
67	dpavlin	61	#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \
68			MPC10X_MAPB_PCI_MEM_START)
69	dpavlin	20
70	dpavlin	61	#endif
71	dpavlin	20
72	dpavlin	61	struct mpc10x_data {
73			int pciirq;
74	dpavlin	20
75	dpavlin	61	struct pci_data *pci_data;
76			uint64_t cur_addr;
77			};
78	dpavlin	20
79
80	dpavlin	61	DEVICE_ACCESS(mpc10x_addr)
81			{
82			struct mpc10x_data *d = extra;
83	dpavlin	20
84	dpavlin	61	if (writeflag == MEM_WRITE) {
85			uint64_t idata = memory_readmax64(cpu, data, len
86			\| MEM_PCI_LITTLE_ENDIAN);
87			int bus, dev, func, reg;
88
89			d->cur_addr = idata;
90			if (idata == 0)
91			return 0;
92
93			/* Decompose the Uni-North tag: */
94			if (idata & 1) {
95			idata &= ~1;
96			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
97	dpavlin	34	} else {
98	dpavlin	61	bus = 0;
99			for (dev=11; dev<32; dev++)
100			if (idata & (1 << dev))
101			break;
102			if (dev == 32)
103			fatal("[ dev_mpc10x_addr_access: no dev? "
104			"idata=0x%08x ]\n", (int)idata);
105	dpavlin	20
106	dpavlin	61	func = (idata >> 8) & 7;
107			reg = idata & 0xff;
108	dpavlin	20	}
109
110	dpavlin	61	bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
111			} else {
112			/* TODO: is returning the current address like this
113			the correct behaviour? */
114			memory_writemax64(cpu, data, len \| MEM_PCI_LITTLE_ENDIAN,
115			d->cur_addr);
116	dpavlin	60	}
117	dpavlin	57
118	dpavlin	58	return 1;
119			}
120	dpavlin	57
121
122	dpavlin	58	DEVICE_ACCESS(mpc10x_data)
123			{
124	dpavlin	61	struct mpc10x_data *d = extra;
125	dpavlin	58	uint64_t idata = 0, odata = 0;
126	dpavlin	57
127	dpavlin	61	if (writeflag == MEM_WRITE)
128	dpavlin	60	idata = memory_readmax64(cpu, data, len\|MEM_PCI_LITTLE_ENDIAN);
129	dpavlin	61
130			bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? &odata :
131			&idata, len, writeflag);
132
133			if (writeflag == MEM_READ)
134	dpavlin	60	memory_writemax64(cpu, data, len\|MEM_PCI_LITTLE_ENDIAN, odata);
135	dpavlin	57
136			return 1;
137			}
138
139	dpavlin	58
140	dpavlin	61	struct pci_data dev_mpc10x_init(struct machine machine, struct memory *mem,
141			uint64_t addr, int isa_irqbase, int pciirq)
142	dpavlin	20	{
143	dpavlin	53	struct mpc10x_data *d;
144	dpavlin	61	// char tmp[100];
145			uint64_t pci_io_offset, pci_mem_offset;
146			uint64_t isa_portbase = 0, isa_membase = 0;
147			uint64_t pci_portbase = 0, pci_membase = 0;
148	dpavlin	20
149	dpavlin	53	CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data)));
150			memset(d, 0, sizeof(struct mpc10x_data));
151	dpavlin	20
152	dpavlin	61	d->pciirq = pciirq;
153	dpavlin	34
154	dpavlin	61	pci_io_offset = 0x00000000ULL;
155			pci_mem_offset = 0x00000000ULL;
156			pci_portbase = 0xd0000000ULL;
157			pci_membase = 0xd1000000ULL;
158			isa_portbase = 0xd2000000ULL;
159			isa_membase = 0xd3000000ULL;
160	dpavlin	34
161	dpavlin	61	/* Create a PCI bus: */
162			d->pci_data = bus_pci_init(machine, "ZZZ_irq_stuff",
163			pci_io_offset, pci_mem_offset,
164			pci_portbase, pci_membase, "XXX_pci_irqbase",
165			isa_portbase, isa_membase, "YYY_isa_irqbase");
166	dpavlin	58
167	dpavlin	61	/* Add the PCI glue for the controller itself: */
168			bus_pci_add(machine, d->pci_data, mem, 0, 0x1f, 0, "mpc10x");
169	dpavlin	58
170	dpavlin	61	/* ADDR and DATA configuration ports: */
171			memory_device_register(mem, "mpc10x_pci_addr", addr + 0xc00000,
172			4, dev_mpc10x_addr_access, d, DM_DEFAULT, NULL);
173			memory_device_register(mem, "mpc10x_pci_data", addr + 0xe00000,
174			8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL);
175	dpavlin	58
176	dpavlin	61	return d->pci_data;
177	dpavlin	20	}
178