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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_le.c,v 1.56 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: LANCE ethernet, as used in DECstations |
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* |
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* This is based on "PMAD-AA TURBOchannel Ethernet Module Functional |
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* Specification". I've tried to keep symbol names in this file to what |
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* the specs use. |
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* |
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* This is what the memory layout looks like on a DECstation 5000/200: |
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* |
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* 0x000000 - 0x0fffff Ethernet SRAM buffer (should be 128KB) |
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* 0x100000 - 0x17ffff LANCE registers |
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* 0x1c0000 - 0x1fffff Ethernet Diagnostic ROM and Station |
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* Address ROM |
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* |
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* The length of the device is set to 0x1c0200, however, because Sprite |
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* tries to read TURBOchannel rom data from 0x1c03f0, and that is provided |
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* by the turbochannel device, not this device. |
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* |
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* |
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* TODO: Error conditions (such as when there are not enough receive |
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* buffers) are not emulated yet. |
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* |
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* (Old bug, but probably still valid: "UDP packets that are too |
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* large are not handled well by the Lance device.") |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "devices.h" |
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#include "emul.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "net.h" |
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|
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#include "if_lereg.h" |
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|
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|
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#define LE_TICK_SHIFT 14 |
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|
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/* #define LE_DEBUG */ |
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/* #define debug fatal */ |
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|
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extern int quiet_mode; |
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|
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#define LE_MODE_LOOP 4 |
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#define LE_MODE_DTX 2 |
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#define LE_MODE_DRX 1 |
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|
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|
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#define N_REGISTERS 4 |
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#define SRAM_SIZE (128*1024) |
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#define ROM_SIZE 32 |
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|
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|
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struct le_data { |
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struct interrupt irq; |
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int irq_asserted; |
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|
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uint64_t buf_start; |
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uint64_t buf_end; |
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int len; |
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|
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uint8_t rom[ROM_SIZE]; |
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|
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int reg_select; |
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uint16_t reg[N_REGISTERS]; |
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|
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unsigned char *sram; |
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|
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/* Initialization block: */ |
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uint32_t init_block_addr; |
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|
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uint16_t mode; |
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uint64_t padr; /* MAC address */ |
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uint64_t ladrf; |
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uint32_t rdra; /* receive descriptor ring address */ |
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int rlen; /* nr of rx descriptors */ |
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uint32_t tdra; /* transmit descriptor ring address */ |
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int tlen; /* nr ot tx descriptors */ |
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|
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/* Current rx and tx descriptor indices: */ |
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int rxp; |
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int txp; |
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|
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unsigned char *tx_packet; |
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int tx_packet_len; |
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|
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unsigned char *rx_packet; |
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int rx_packet_len; |
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int rx_packet_offset; |
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int rx_middle_bit; |
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}; |
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|
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|
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/* |
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* le_read_16bit(): |
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* |
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* Read a 16-bit word from the SRAM. |
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*/ |
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static uint64_t le_read_16bit(struct le_data *d, int addr) |
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{ |
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/* TODO: This is for little endian only */ |
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int x = d->sram[addr & (SRAM_SIZE-1)] + |
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(d->sram[(addr+1) & (SRAM_SIZE-1)] << 8); |
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return x; |
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} |
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|
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|
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/* |
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* le_write_16bit(): |
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* |
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* Write a 16-bit word to the SRAM. |
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*/ |
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static void le_write_16bit(struct le_data *d, int addr, uint16_t x) |
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{ |
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/* TODO: This is for little endian only */ |
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d->sram[addr & (SRAM_SIZE-1)] = x & 0xff; |
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d->sram[(addr+1) & (SRAM_SIZE-1)] = (x >> 8) & 0xff; |
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} |
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|
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|
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/* |
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* le_chip_init(): |
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* |
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* Initialize data structures by reading an 'initialization block' from the |
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* SRAM. |
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*/ |
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static void le_chip_init(struct le_data *d) |
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{ |
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d->init_block_addr = (d->reg[1] & 0xffff) + ((d->reg[2] & 0xff) << 16); |
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if (d->init_block_addr & 1) |
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fatal("[ le: WARNING! initialization block address " |
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"not word aligned? ]\n"); |
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|
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debug("[ le: d->init_block_addr = 0x%06x ]\n", d->init_block_addr); |
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|
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d->mode = le_read_16bit(d, d->init_block_addr + 0); |
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d->padr = le_read_16bit(d, d->init_block_addr + 2); |
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d->padr += (le_read_16bit(d, d->init_block_addr + 4) << 16); |
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d->padr += (le_read_16bit(d, d->init_block_addr + 6) << 32); |
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d->ladrf = le_read_16bit(d, d->init_block_addr + 8); |
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d->ladrf += (le_read_16bit(d, d->init_block_addr + 10) << 16); |
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d->ladrf += (le_read_16bit(d, d->init_block_addr + 12) << 32); |
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d->ladrf += (le_read_16bit(d, d->init_block_addr + 14) << 48); |
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d->rdra = le_read_16bit(d, d->init_block_addr + 16); |
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d->rdra += ((le_read_16bit(d, d->init_block_addr + 18) & 0xff) << 16); |
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d->rlen = 1 << ((le_read_16bit(d, d->init_block_addr + 18) >> 13) & 7); |
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d->tdra = le_read_16bit(d, d->init_block_addr + 20); |
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d->tdra += ((le_read_16bit(d, d->init_block_addr + 22) & 0xff) << 16); |
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d->tlen = 1 << ((le_read_16bit(d, d->init_block_addr + 22) >> 13) & 7); |
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|
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debug("[ le: DEBUG: mode %04x ]\n", d->mode); |
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debug("[ le: DEBUG: padr %016llx ]\n", (long long)d->padr); |
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debug("[ le: DEBUG: ladrf %016llx ]\n", (long long)d->ladrf); |
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debug("[ le: DEBUG: rdra %06llx ]\n", d->rdra); |
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debug("[ le: DEBUG: rlen %3i ]\n", d->rlen); |
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debug("[ le: DEBUG: tdra %06llx ]\n", d->tdra); |
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debug("[ le: DEBUG: tlen %3i ]\n", d->tlen); |
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|
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/* Set TXON and RXON, unless they are disabled by 'mode': */ |
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if (d->mode & LE_MODE_DTX) |
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d->reg[0] &= ~LE_TXON; |
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else |
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d->reg[0] |= LE_TXON; |
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|
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if (d->mode & LE_MODE_DRX) |
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d->reg[0] &= ~LE_RXON; |
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else |
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d->reg[0] |= LE_RXON; |
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|
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/* Go to the start of the descriptor rings: */ |
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d->rxp = d->txp = 0; |
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|
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/* Set IDON and reset the INIT bit when we are done. */ |
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d->reg[0] |= LE_IDON; |
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d->reg[0] &= ~LE_INIT; |
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|
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/* Free any old packets: */ |
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if (d->tx_packet != NULL) |
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free(d->tx_packet); |
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d->tx_packet = NULL; |
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d->tx_packet_len = 0; |
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|
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if (d->rx_packet != NULL) |
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free(d->rx_packet); |
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d->rx_packet = NULL; |
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d->rx_packet_len = 0; |
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d->rx_packet_offset = 0; |
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d->rx_middle_bit = 0; |
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} |
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|
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|
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/* |
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* le_tx(): |
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* |
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* Check the transmitter descriptor ring for buffers that are owned by the |
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* Lance chip (that is, buffers that are to be transmitted). |
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* |
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* This routine should only be called if TXON is enabled. |
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*/ |
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static void le_tx(struct net *net, struct le_data *d) |
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{ |
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int start_txp = d->txp; |
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uint16_t tx_descr[4]; |
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int stp, enp, cur_packet_offset; |
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size_t i; |
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uint32_t bufaddr, buflen; |
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|
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/* TODO: This is just a guess: */ |
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d->reg[0] &= ~LE_TDMD; |
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|
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do { |
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/* Load the 8 descriptor bytes: */ |
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tx_descr[0] = le_read_16bit(d, d->tdra + d->txp*8 + 0); |
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tx_descr[1] = le_read_16bit(d, d->tdra + d->txp*8 + 2); |
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tx_descr[2] = le_read_16bit(d, d->tdra + d->txp*8 + 4); |
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tx_descr[3] = le_read_16bit(d, d->tdra + d->txp*8 + 6); |
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|
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bufaddr = tx_descr[0] + ((tx_descr[1] & 0xff) << 16); |
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stp = tx_descr[1] & LE_STP? 1 : 0; |
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enp = tx_descr[1] & LE_ENP? 1 : 0; |
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buflen = 4096 - (tx_descr[2] & 0xfff); |
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|
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/* |
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* Check the OWN bit. If it is zero, then this buffer is |
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* not ready to be transmitted yet. Also check the '1111' |
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* mark, and make sure that byte-count is reasonable. |
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*/ |
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if (!(tx_descr[1] & LE_OWN)) |
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return; |
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if ((tx_descr[2] & 0xf000) != 0xf000) |
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return; |
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if (buflen < 12 || buflen > 1900) { |
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fatal("[ le_tx(): buflen = %i ]\n", buflen); |
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return; |
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} |
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|
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debug("[ le_tx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x " |
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"=> addr=0x%06x, len=%i bytes, STP=%i ENP=%i ]\n", d->txp, |
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tx_descr[0], tx_descr[1], tx_descr[2], tx_descr[3], |
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bufaddr, buflen, stp, enp); |
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|
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if (d->tx_packet == NULL && !stp) { |
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fatal("[ le_tx(): !stp but tx_packet == NULL ]\n"); |
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return; |
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} |
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|
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if (d->tx_packet != NULL && stp) { |
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fatal("[ le_tx(): stp but tx_packet != NULL ]\n"); |
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free(d->tx_packet); |
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d->tx_packet = NULL; |
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d->tx_packet_len = 0; |
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} |
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|
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/* Where to write to in the tx_packet: */ |
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cur_packet_offset = d->tx_packet_len; |
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|
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/* Start of a new packet: */ |
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if (stp) { |
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d->tx_packet_len = buflen; |
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CHECK_ALLOCATION(d->tx_packet = malloc(buflen)); |
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} else { |
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d->tx_packet_len += buflen; |
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CHECK_ALLOCATION(d->tx_packet = |
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realloc(d->tx_packet, d->tx_packet_len)); |
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} |
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|
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/* Copy data from SRAM into the tx packet: */ |
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for (i=0; i<buflen; i++) { |
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unsigned char ch; |
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ch = d->sram[(bufaddr + i) & (SRAM_SIZE-1)]; |
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d->tx_packet[cur_packet_offset + i] = ch; |
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} |
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|
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/* |
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* Is this the last buffer in a packet? Then transmit |
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* it, cause an interrupt, and free the memory used by |
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* the packet. |
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*/ |
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if (enp) { |
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net_ethernet_tx(net, d, d->tx_packet, d->tx_packet_len); |
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|
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free(d->tx_packet); |
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d->tx_packet = NULL; |
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d->tx_packet_len = 0; |
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|
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d->reg[0] |= LE_TINT; |
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} |
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|
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/* Clear the OWN bit: */ |
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tx_descr[1] &= ~LE_OWN; |
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|
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/* Write back the descriptor to SRAM: */ |
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le_write_16bit(d, d->tdra + d->txp*8 + 2, tx_descr[1]); |
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le_write_16bit(d, d->tdra + d->txp*8 + 4, tx_descr[2]); |
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le_write_16bit(d, d->tdra + d->txp*8 + 6, tx_descr[3]); |
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|
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/* Go to the next descriptor: */ |
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d->txp ++; |
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if (d->txp >= d->tlen) |
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d->txp = 0; |
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} while (d->txp != start_txp); |
335 |
|
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/* We are here if all descriptors were taken care of. */ |
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fatal("[ le_tx(): all TX descriptors used up? ]\n"); |
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} |
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|
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|
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/* |
342 |
* le_rx(): |
343 |
* |
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* This routine should only be called if RXON is enabled. |
345 |
*/ |
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static void le_rx(struct net *net, struct le_data *d) |
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{ |
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int start_rxp = d->rxp; |
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size_t i; |
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uint16_t rx_descr[4]; |
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uint32_t bufaddr, buflen; |
352 |
|
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do { |
354 |
if (d->rx_packet == NULL) |
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return; |
356 |
|
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/* Load the 8 descriptor bytes: */ |
358 |
rx_descr[0] = le_read_16bit(d, d->rdra + d->rxp*8 + 0); |
359 |
rx_descr[1] = le_read_16bit(d, d->rdra + d->rxp*8 + 2); |
360 |
rx_descr[2] = le_read_16bit(d, d->rdra + d->rxp*8 + 4); |
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rx_descr[3] = le_read_16bit(d, d->rdra + d->rxp*8 + 6); |
362 |
|
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bufaddr = rx_descr[0] + ((rx_descr[1] & 0xff) << 16); |
364 |
buflen = 4096 - (rx_descr[2] & 0xfff); |
365 |
|
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/* |
367 |
* Check the OWN bit. If it is zero, then this buffer is |
368 |
* not ready to receive data yet. Also check the '1111' |
369 |
* mark, and make sure that byte-count is reasonable. |
370 |
*/ |
371 |
if (!(rx_descr[1] & LE_OWN)) |
372 |
return; |
373 |
if ((rx_descr[2] & 0xf000) != 0xf000) |
374 |
return; |
375 |
if (buflen < 12 || buflen > 1900) { |
376 |
fatal("[ le_rx(): buflen = %i ]\n", buflen); |
377 |
return; |
378 |
} |
379 |
|
380 |
debug("[ le_rx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x " |
381 |
"=> addr=0x%06x, len=%i bytes ]\n", d->rxp, |
382 |
rx_descr[0], rx_descr[1], rx_descr[2], rx_descr[3], |
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bufaddr, buflen); |
384 |
|
385 |
/* Copy data from the packet into SRAM: */ |
386 |
for (i=0; i<buflen; i++) { |
387 |
if (d->rx_packet_offset+(ssize_t)i >= d->rx_packet_len) |
388 |
break; |
389 |
d->sram[(bufaddr + i) & (SRAM_SIZE-1)] = |
390 |
d->rx_packet[d->rx_packet_offset + i]; |
391 |
} |
392 |
|
393 |
/* Here, i is the number of bytes copied. */ |
394 |
d->rx_packet_offset += i; |
395 |
|
396 |
/* Set the ENP bit if this was the end of a packet: */ |
397 |
if (d->rx_packet_offset >= d->rx_packet_len) { |
398 |
rx_descr[1] |= LE_ENP; |
399 |
|
400 |
/* |
401 |
* NOTE: The Lance documentation that I have read |
402 |
* says _NOTHING_ about the length being 4 more than |
403 |
* the length of the data. You can guess how |
404 |
* surprised I was when I saw the following in |
405 |
* NetBSD (dev/ic/am7990.c): |
406 |
* |
407 |
* lance_read(sc, LE_RBUFADDR(sc, bix), |
408 |
* (int)rmd.rmd3 - 4); |
409 |
*/ |
410 |
rx_descr[3] &= ~0xfff; |
411 |
rx_descr[3] |= d->rx_packet_len + 4; |
412 |
|
413 |
free(d->rx_packet); |
414 |
d->rx_packet = NULL; |
415 |
d->rx_packet_len = 0; |
416 |
d->rx_packet_offset = 0; |
417 |
d->rx_middle_bit = 0; |
418 |
|
419 |
d->reg[0] |= LE_RINT; |
420 |
} |
421 |
|
422 |
/* Set the STP bit if this was the start of a packet: */ |
423 |
if (!d->rx_middle_bit) { |
424 |
rx_descr[1] |= LE_STP; |
425 |
|
426 |
/* Are we continuing on this packet? */ |
427 |
if (d->rx_packet != NULL) |
428 |
d->rx_middle_bit = 1; |
429 |
} |
430 |
|
431 |
/* Clear the OWN bit: */ |
432 |
rx_descr[1] &= ~LE_OWN; |
433 |
|
434 |
/* Write back the descriptor to SRAM: */ |
435 |
le_write_16bit(d, d->rdra + d->rxp*8 + 2, rx_descr[1]); |
436 |
le_write_16bit(d, d->rdra + d->rxp*8 + 4, rx_descr[2]); |
437 |
le_write_16bit(d, d->rdra + d->rxp*8 + 6, rx_descr[3]); |
438 |
|
439 |
/* Go to the next descriptor: */ |
440 |
d->rxp ++; |
441 |
if (d->rxp >= d->rlen) |
442 |
d->rxp = 0; |
443 |
} while (d->rxp != start_rxp); |
444 |
|
445 |
/* We are here if all descriptors were taken care of. */ |
446 |
fatal("[ le_rx(): all RX descriptors used up? ]\n"); |
447 |
} |
448 |
|
449 |
|
450 |
/* |
451 |
* le_register_fix(): |
452 |
*/ |
453 |
static void le_register_fix(struct net *net, struct le_data *d) |
454 |
{ |
455 |
/* Init with new Initialization block, if needed. */ |
456 |
if (d->reg[0] & LE_INIT) |
457 |
le_chip_init(d); |
458 |
|
459 |
#ifdef LE_DEBUG |
460 |
{ |
461 |
static int x = 1234; |
462 |
if (x != d->reg[0]) { |
463 |
debug("[ le reg[0] = 0x%04x ]\n", d->reg[0]); |
464 |
x = d->reg[0]; |
465 |
} |
466 |
} |
467 |
#endif |
468 |
|
469 |
/* |
470 |
* If the receiver is on: |
471 |
* If there is a current rx_packet, try to receive it into the |
472 |
* Lance buffers. Then try to receive any additional packets. |
473 |
*/ |
474 |
if (d->reg[0] & LE_RXON) { |
475 |
do { |
476 |
if (d->rx_packet != NULL) |
477 |
/* Try to receive the packet: */ |
478 |
le_rx(net, d); |
479 |
|
480 |
if (d->rx_packet != NULL) |
481 |
/* If the packet wasn't fully received, |
482 |
then abort for now. */ |
483 |
break; |
484 |
|
485 |
if (d->rx_packet == NULL && |
486 |
net_ethernet_rx_avail(net, d)) |
487 |
net_ethernet_rx(net, d, |
488 |
&d->rx_packet, &d->rx_packet_len); |
489 |
} while (d->rx_packet != NULL); |
490 |
} |
491 |
|
492 |
/* If the transmitter is on, check for outgoing buffers: */ |
493 |
if (d->reg[0] & LE_TXON) |
494 |
le_tx(net, d); |
495 |
|
496 |
/* SERR should be the OR of BABL, CERR, MISS, and MERR: */ |
497 |
d->reg[0] &= ~LE_SERR; |
498 |
if (d->reg[0] & (LE_BABL | LE_CERR | LE_MISS | LE_MERR)) |
499 |
d->reg[0] |= LE_SERR; |
500 |
|
501 |
/* INTR should be the OR of BABL, MISS, MERR, RINT, TINT, IDON: */ |
502 |
d->reg[0] &= ~LE_INTR; |
503 |
if (d->reg[0] & (LE_BABL | LE_MISS | LE_MERR | LE_RINT | |
504 |
LE_TINT | LE_IDON)) |
505 |
d->reg[0] |= LE_INTR; |
506 |
|
507 |
/* The MERR bit clears some bits: */ |
508 |
if (d->reg[0] & LE_MERR) |
509 |
d->reg[0] &= ~(LE_RXON | LE_TXON); |
510 |
|
511 |
/* The STOP bit clears a lot of stuff: */ |
512 |
#if 0 |
513 |
/* According to the LANCE manual: (doesn't work with Ultrix) */ |
514 |
if (d->reg[0] & LE_STOP) |
515 |
d->reg[0] &= ~(LE_SERR | LE_BABL | LE_CERR | LE_MISS | LE_MERR |
516 |
| LE_RINT | LE_TINT | LE_IDON | LE_INTR | LE_INEA |
517 |
| LE_RXON | LE_TXON | LE_TDMD); |
518 |
#else |
519 |
/* Works with Ultrix: */ |
520 |
if (d->reg[0] & LE_STOP) |
521 |
d->reg[0] &= ~(LE_IDON); |
522 |
#endif |
523 |
} |
524 |
|
525 |
|
526 |
DEVICE_TICK(le) |
527 |
{ |
528 |
struct le_data *d = extra; |
529 |
int new_assert; |
530 |
|
531 |
le_register_fix(cpu->machine->emul->net, d); |
532 |
|
533 |
new_assert = (d->reg[0] & LE_INTR) && (d->reg[0] & LE_INEA); |
534 |
|
535 |
if (new_assert && !d->irq_asserted) |
536 |
INTERRUPT_ASSERT(d->irq); |
537 |
if (d->irq_asserted && !new_assert) |
538 |
INTERRUPT_DEASSERT(d->irq); |
539 |
|
540 |
d->irq_asserted = new_assert; |
541 |
} |
542 |
|
543 |
|
544 |
/* |
545 |
* le_register_write(): |
546 |
* |
547 |
* This function is called when the value 'x' is written to register 'r'. |
548 |
*/ |
549 |
void le_register_write(struct le_data *d, int r, uint32_t x) |
550 |
{ |
551 |
switch (r) { |
552 |
case 0: /* CSR0: */ |
553 |
/* Some bits are write-one-to-clear: */ |
554 |
if (x & LE_BABL) |
555 |
d->reg[r] &= ~LE_BABL; |
556 |
if (x & LE_CERR) |
557 |
d->reg[r] &= ~LE_CERR; |
558 |
if (x & LE_MISS) |
559 |
d->reg[r] &= ~LE_MISS; |
560 |
if (x & LE_MERR) |
561 |
d->reg[r] &= ~LE_MERR; |
562 |
if (x & LE_RINT) |
563 |
d->reg[r] &= ~LE_RINT; |
564 |
if (x & LE_TINT) |
565 |
d->reg[r] &= ~LE_TINT; |
566 |
if (x & LE_IDON) |
567 |
d->reg[r] &= ~LE_IDON; |
568 |
|
569 |
/* Some bits are write-only settable, not clearable: */ |
570 |
if (x & LE_TDMD) |
571 |
d->reg[r] |= LE_TDMD; |
572 |
if (x & LE_STRT) { |
573 |
d->reg[r] |= LE_STRT; |
574 |
d->reg[r] &= ~LE_STOP; |
575 |
} |
576 |
if (x & LE_INIT) { |
577 |
if (!(d->reg[r] & LE_STOP)) |
578 |
fatal("[ le: attempt to INIT before" |
579 |
" STOPped! ]\n"); |
580 |
d->reg[r] |= LE_INIT; |
581 |
d->reg[r] &= ~LE_STOP; |
582 |
} |
583 |
if (x & LE_STOP) { |
584 |
d->reg[r] |= LE_STOP; |
585 |
/* STOP takes precedence over STRT and INIT: */ |
586 |
d->reg[r] &= ~(LE_STRT | LE_INIT); |
587 |
} |
588 |
|
589 |
/* Some bits get through, both settable and clearable: */ |
590 |
d->reg[r] &= ~LE_INEA; |
591 |
d->reg[r] |= (x & LE_INEA); |
592 |
break; |
593 |
|
594 |
default: |
595 |
/* CSR1, CSR2, and CSR3: */ |
596 |
d->reg[r] = x; |
597 |
} |
598 |
} |
599 |
|
600 |
|
601 |
DEVICE_ACCESS(le_sram) |
602 |
{ |
603 |
struct le_data *d = extra; |
604 |
size_t i; |
605 |
int retval; |
606 |
|
607 |
#ifdef LE_DEBUG |
608 |
if (writeflag == MEM_WRITE) { |
609 |
fatal("[ le_sram: write to addr 0x%06x: ", (int)relative_addr); |
610 |
for (i=0; i<len; i++) |
611 |
fatal("%02x ", data[i]); |
612 |
fatal("]\n"); |
613 |
} |
614 |
#endif |
615 |
|
616 |
/* Read/write of the SRAM: */ |
617 |
if (relative_addr < SRAM_SIZE && relative_addr + len <= SRAM_SIZE) { |
618 |
if (writeflag == MEM_READ) { |
619 |
memcpy(data, d->sram + relative_addr, len); |
620 |
if (!quiet_mode) { |
621 |
debug("[ le: read from SRAM offset 0x%05x:", |
622 |
relative_addr); |
623 |
for (i=0; i<len; i++) |
624 |
debug(" %02x", data[i]); |
625 |
debug(" ]\n"); |
626 |
} |
627 |
retval = 9; /* 9 cycles */ |
628 |
} else { |
629 |
memcpy(d->sram + relative_addr, data, len); |
630 |
if (!quiet_mode) { |
631 |
debug("[ le: write to SRAM offset 0x%05x:", |
632 |
relative_addr); |
633 |
for (i=0; i<len; i++) |
634 |
debug(" %02x", data[i]); |
635 |
debug(" ]\n"); |
636 |
} |
637 |
retval = 6; /* 6 cycles */ |
638 |
} |
639 |
return retval; |
640 |
} |
641 |
|
642 |
return 0; |
643 |
} |
644 |
|
645 |
|
646 |
DEVICE_ACCESS(le) |
647 |
{ |
648 |
struct le_data *d = extra; |
649 |
uint64_t idata = 0, odata = 0; |
650 |
int retval = 1; |
651 |
size_t i; |
652 |
|
653 |
if (writeflag == MEM_WRITE) |
654 |
idata = memory_readmax64(cpu, data, len); |
655 |
|
656 |
#ifdef LE_DEBUG |
657 |
if (writeflag == MEM_WRITE) { |
658 |
fatal("[ le: write to addr 0x%06x: ", (int)relative_addr); |
659 |
for (i=0; i<len; i++) |
660 |
fatal("%02x ", data[i]); |
661 |
fatal("]\n"); |
662 |
} |
663 |
#endif |
664 |
|
665 |
/* Read from station's ROM (ethernet address): */ |
666 |
if (relative_addr >= 0xc0000 && relative_addr <= 0xfffff) { |
667 |
uint32_t a; |
668 |
int j = (relative_addr & 0xff) / 4; |
669 |
a = d->rom[j & (ROM_SIZE-1)]; |
670 |
|
671 |
if (writeflag == MEM_READ) { |
672 |
odata = (a << 24) + (a << 16) + (a << 8) + a; |
673 |
} else { |
674 |
fatal("[ le: WRITE to ethernet addr (%08lx):", |
675 |
(long)relative_addr); |
676 |
for (i=0; i<len; i++) |
677 |
fatal(" %02x", data[i]); |
678 |
fatal(" ]\n"); |
679 |
} |
680 |
|
681 |
retval = 13; /* 13 cycles */ |
682 |
goto do_return; |
683 |
} |
684 |
|
685 |
|
686 |
switch (relative_addr) { |
687 |
|
688 |
/* Register read/write: */ |
689 |
case 0: |
690 |
if (writeflag==MEM_READ) { |
691 |
odata = d->reg[d->reg_select]; |
692 |
if (!quiet_mode) |
693 |
debug("[ le: read from register 0x%02x: 0x" |
694 |
"%02x ]\n", d->reg_select, (int)odata); |
695 |
/* |
696 |
* A read from csr1..3 should return "undefined" |
697 |
* result if the stop bit is set. However, Ultrix |
698 |
* seems to do just that, so let's _not_ print |
699 |
* a warning here. |
700 |
*/ |
701 |
} else { |
702 |
if (!quiet_mode) |
703 |
debug("[ le: write to register 0x%02x: 0x" |
704 |
"%02x ]\n", d->reg_select, (int)idata); |
705 |
/* |
706 |
* A write to from csr1..3 when the stop bit is |
707 |
* set should be ignored. However, Ultrix writes |
708 |
* even if the stop bit is set, so let's _not_ |
709 |
* print a warning about it. |
710 |
*/ |
711 |
le_register_write(d, d->reg_select, idata); |
712 |
} |
713 |
break; |
714 |
|
715 |
/* Register select: */ |
716 |
case 4: |
717 |
if (writeflag==MEM_READ) { |
718 |
odata = d->reg_select; |
719 |
if (!quiet_mode) |
720 |
debug("[ le: read from register select: " |
721 |
"0x%02x ]\n", (int)odata); |
722 |
} else { |
723 |
if (!quiet_mode) |
724 |
debug("[ le: write to register select: " |
725 |
"0x%02x ]\n", (int)idata); |
726 |
d->reg_select = idata & (N_REGISTERS - 1); |
727 |
if (idata >= N_REGISTERS) |
728 |
fatal("[ le: WARNING! register select %i " |
729 |
"(max is %i) ]\n", idata, N_REGISTERS - 1); |
730 |
} |
731 |
break; |
732 |
|
733 |
default: |
734 |
if (writeflag==MEM_READ) { |
735 |
fatal("[ le: read from UNIMPLEMENTED addr 0x%06x ]\n", |
736 |
(int)relative_addr); |
737 |
} else { |
738 |
fatal("[ le: write to UNIMPLEMENTED addr 0x%06x: " |
739 |
"0x%08x ]\n", (int)relative_addr, (int)idata); |
740 |
} |
741 |
} |
742 |
|
743 |
do_return: |
744 |
if (writeflag == MEM_READ) { |
745 |
memory_writemax64(cpu, data, len, odata); |
746 |
#ifdef LE_DEBUG |
747 |
fatal("[ le: read from addr 0x%06x: 0x%08x ]\n", |
748 |
relative_addr, odata); |
749 |
#endif |
750 |
} |
751 |
|
752 |
dev_le_tick(cpu, extra); |
753 |
|
754 |
return retval; |
755 |
} |
756 |
|
757 |
|
758 |
/* |
759 |
* dev_le_init(): |
760 |
*/ |
761 |
void dev_le_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, |
762 |
uint64_t buf_start, uint64_t buf_end, char *irq_path, int len) |
763 |
{ |
764 |
char *name2; |
765 |
size_t nlen = 55; |
766 |
struct le_data *d; |
767 |
|
768 |
CHECK_ALLOCATION(d = malloc(sizeof(struct le_data))); |
769 |
memset(d, 0, sizeof(struct le_data)); |
770 |
|
771 |
INTERRUPT_CONNECT(irq_path, d->irq); |
772 |
|
773 |
CHECK_ALLOCATION(d->sram = malloc(SRAM_SIZE)); |
774 |
memset(d->sram, 0, SRAM_SIZE); |
775 |
|
776 |
/* TODO: Are these actually used yet? */ |
777 |
d->len = len; |
778 |
d->buf_start = buf_start; |
779 |
d->buf_end = buf_end; |
780 |
|
781 |
/* Initial register contents: */ |
782 |
d->reg[0] = LE_STOP; |
783 |
|
784 |
d->tx_packet = NULL; |
785 |
d->rx_packet = NULL; |
786 |
|
787 |
/* ROM (including the MAC address): */ |
788 |
net_generate_unique_mac(machine, &d->rom[0]); |
789 |
|
790 |
/* Copies of the MAC address and a test pattern: */ |
791 |
d->rom[10] = d->rom[21] = d->rom[5]; |
792 |
d->rom[11] = d->rom[20] = d->rom[4]; |
793 |
d->rom[12] = d->rom[19] = d->rom[3]; |
794 |
d->rom[7] = d->rom[8] = d->rom[23] = |
795 |
d->rom[13] = d->rom[18] = d->rom[2]; |
796 |
d->rom[6] = d->rom[9] = d->rom[22] = |
797 |
d->rom[14] = d->rom[17] = d->rom[1]; |
798 |
d->rom[15] = d->rom[16] = d->rom[0]; |
799 |
d->rom[24] = d->rom[28] = 0xff; |
800 |
d->rom[25] = d->rom[29] = 0x00; |
801 |
d->rom[26] = d->rom[30] = 0x55; |
802 |
d->rom[27] = d->rom[31] = 0xaa; |
803 |
|
804 |
memory_device_register(mem, "le_sram", baseaddr, |
805 |
SRAM_SIZE, dev_le_sram_access, (void *)d, |
806 |
DM_DYNTRANS_OK | DM_DYNTRANS_WRITE_OK |
807 |
| DM_READS_HAVE_NO_SIDE_EFFECTS, d->sram); |
808 |
|
809 |
CHECK_ALLOCATION(name2 = malloc(nlen)); |
810 |
snprintf(name2, nlen, "le [%02x:%02x:%02x:%02x:%02x:%02x]", |
811 |
d->rom[0], d->rom[1], d->rom[2], d->rom[3], d->rom[4], d->rom[5]); |
812 |
|
813 |
memory_device_register(mem, name2, baseaddr + 0x100000, |
814 |
len - 0x100000, dev_le_access, (void *)d, DM_DEFAULT, NULL); |
815 |
|
816 |
machine_add_tickfunction(machine, dev_le_tick, d, LE_TICK_SHIFT); |
817 |
|
818 |
net_add_nic(machine->emul->net, d, &d->rom[0]); |
819 |
} |
820 |
|