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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_le.c,v 1.43 2005/07/27 06:57:34 debug Exp $ |
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* |
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* LANCE ethernet, as used in DECstations. |
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* |
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* This is based on "PMAD-AA TURBOchannel Ethernet Module Functional |
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* Specification". I've tried to keep symbol names in this file to what |
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* the specs use. |
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* |
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* This is what the memory layout looks like on a DECstation 5000/200: |
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* |
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* 0x000000 - 0x0fffff Ethernet SRAM buffer (should be 128KB) |
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* 0x100000 - 0x17ffff LANCE registers |
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* 0x1c0000 - 0x1fffff Ethernet Diagnostic ROM and Station |
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* Address ROM |
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* |
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* The length of the device is set to 0x1c0200, however, because Sprite |
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* tries to read TURBOchannel rom data from 0x1c03f0, and that is provided |
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* by the turbochannel device, not this device. |
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* |
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* |
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* TODO: Error conditions (such as when there are not enough receive |
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* buffers) are not emulated yet. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "devices.h" |
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#include "emul.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "net.h" |
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|
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#include "if_lereg.h" |
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|
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|
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#define LE_TICK_SHIFT 14 |
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|
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/* #define LE_DEBUG */ |
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/* #define debug fatal */ |
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|
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extern int quiet_mode; |
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|
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#define LE_MODE_LOOP 4 |
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#define LE_MODE_DTX 2 |
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#define LE_MODE_DRX 1 |
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|
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|
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#define N_REGISTERS 4 |
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#define SRAM_SIZE (128*1024) |
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#define ROM_SIZE 32 |
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|
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|
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struct le_data { |
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int irq_nr; |
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|
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uint64_t buf_start; |
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uint64_t buf_end; |
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int len; |
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|
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uint8_t rom[ROM_SIZE]; |
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|
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int reg_select; |
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uint16_t reg[N_REGISTERS]; |
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|
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unsigned char *sram; |
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|
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/* Initialization block: */ |
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uint32_t init_block_addr; |
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|
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uint16_t mode; |
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uint64_t padr; /* MAC address */ |
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uint64_t ladrf; |
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uint32_t rdra; /* receive descriptor ring address */ |
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int rlen; /* nr of rx descriptors */ |
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uint32_t tdra; /* transmit descriptor ring address */ |
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int tlen; /* nr ot tx descriptors */ |
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|
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/* Current rx and tx descriptor indices: */ |
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int rxp; |
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int txp; |
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|
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unsigned char *tx_packet; |
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int tx_packet_len; |
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|
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unsigned char *rx_packet; |
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int rx_packet_len; |
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int rx_packet_offset; |
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int rx_middle_bit; |
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}; |
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|
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|
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/* |
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* le_read_16bit(): |
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* |
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* Read a 16-bit word from the SRAM. |
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*/ |
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static uint64_t le_read_16bit(struct le_data *d, int addr) |
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{ |
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/* TODO: This is for little endian only */ |
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int x = d->sram[addr & (SRAM_SIZE-1)] + |
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(d->sram[(addr+1) & (SRAM_SIZE-1)] << 8); |
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return x; |
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} |
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|
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|
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/* |
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* le_write_16bit(): |
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* |
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* Write a 16-bit word to the SRAM. |
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*/ |
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static void le_write_16bit(struct le_data *d, int addr, uint16_t x) |
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{ |
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/* TODO: This is for little endian only */ |
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d->sram[addr & (SRAM_SIZE-1)] = x & 0xff; |
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d->sram[(addr+1) & (SRAM_SIZE-1)] = (x >> 8) & 0xff; |
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} |
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|
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|
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/* |
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* le_chip_init(): |
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* |
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* Initialize data structures by reading an 'initialization block' from the |
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* SRAM. |
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*/ |
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static void le_chip_init(struct le_data *d) |
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{ |
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d->init_block_addr = (d->reg[1] & 0xffff) + ((d->reg[2] & 0xff) << 16); |
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if (d->init_block_addr & 1) |
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fatal("[ le: WARNING! initialization block address " |
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"not word aligned? ]\n"); |
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|
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debug("[ le: d->init_block_addr = 0x%06x ]\n", d->init_block_addr); |
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|
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d->mode = le_read_16bit(d, d->init_block_addr + 0); |
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d->padr = le_read_16bit(d, d->init_block_addr + 2); |
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d->padr += (le_read_16bit(d, d->init_block_addr + 4) << 16); |
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d->padr += (le_read_16bit(d, d->init_block_addr + 6) << 32); |
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d->ladrf = le_read_16bit(d, d->init_block_addr + 8); |
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d->ladrf += (le_read_16bit(d, d->init_block_addr + 10) << 16); |
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d->ladrf += (le_read_16bit(d, d->init_block_addr + 12) << 32); |
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d->ladrf += (le_read_16bit(d, d->init_block_addr + 14) << 48); |
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d->rdra = le_read_16bit(d, d->init_block_addr + 16); |
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d->rdra += ((le_read_16bit(d, d->init_block_addr + 18) & 0xff) << 16); |
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d->rlen = 1 << ((le_read_16bit(d, d->init_block_addr + 18) >> 13) & 7); |
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d->tdra = le_read_16bit(d, d->init_block_addr + 20); |
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d->tdra += ((le_read_16bit(d, d->init_block_addr + 22) & 0xff) << 16); |
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d->tlen = 1 << ((le_read_16bit(d, d->init_block_addr + 22) >> 13) & 7); |
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|
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debug("[ le: DEBUG: mode %04x ]\n", d->mode); |
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debug("[ le: DEBUG: padr %016llx ]\n", (long long)d->padr); |
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debug("[ le: DEBUG: ladrf %016llx ]\n", (long long)d->ladrf); |
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debug("[ le: DEBUG: rdra %06llx ]\n", d->rdra); |
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debug("[ le: DEBUG: rlen %3i ]\n", d->rlen); |
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debug("[ le: DEBUG: tdra %06llx ]\n", d->tdra); |
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debug("[ le: DEBUG: tlen %3i ]\n", d->tlen); |
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|
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/* Set TXON and RXON, unless they are disabled by 'mode': */ |
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if (d->mode & LE_MODE_DTX) |
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d->reg[0] &= ~LE_TXON; |
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else |
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d->reg[0] |= LE_TXON; |
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|
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if (d->mode & LE_MODE_DRX) |
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d->reg[0] &= ~LE_RXON; |
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else |
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d->reg[0] |= LE_RXON; |
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|
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/* Go to the start of the descriptor rings: */ |
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d->rxp = d->txp = 0; |
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|
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/* Set IDON and reset the INIT bit when we are done. */ |
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d->reg[0] |= LE_IDON; |
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d->reg[0] &= ~LE_INIT; |
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|
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/* Free any old packets: */ |
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if (d->tx_packet != NULL) |
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free(d->tx_packet); |
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d->tx_packet = NULL; |
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d->tx_packet_len = 0; |
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|
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if (d->rx_packet != NULL) |
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free(d->rx_packet); |
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d->rx_packet = NULL; |
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d->rx_packet_len = 0; |
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d->rx_packet_offset = 0; |
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d->rx_middle_bit = 0; |
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} |
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|
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|
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/* |
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* le_tx(): |
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* |
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* Check the transmitter descriptor ring for buffers that are owned by the |
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* Lance chip (that is, buffers that are to be transmitted). |
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* |
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* This routine should only be called if TXON is enabled. |
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*/ |
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static void le_tx(struct net *net, struct le_data *d) |
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{ |
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int start_txp = d->txp; |
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uint16_t tx_descr[4]; |
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int stp, enp, i, cur_packet_offset; |
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uint32_t bufaddr, buflen; |
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|
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/* TODO: This is just a guess: */ |
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d->reg[0] &= ~LE_TDMD; |
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|
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do { |
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/* Load the 8 descriptor bytes: */ |
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tx_descr[0] = le_read_16bit(d, d->tdra + d->txp*8 + 0); |
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tx_descr[1] = le_read_16bit(d, d->tdra + d->txp*8 + 2); |
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tx_descr[2] = le_read_16bit(d, d->tdra + d->txp*8 + 4); |
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tx_descr[3] = le_read_16bit(d, d->tdra + d->txp*8 + 6); |
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|
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bufaddr = tx_descr[0] + ((tx_descr[1] & 0xff) << 16); |
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stp = tx_descr[1] & LE_STP? 1 : 0; |
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enp = tx_descr[1] & LE_ENP? 1 : 0; |
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buflen = 4096 - (tx_descr[2] & 0xfff); |
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|
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/* |
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* Check the OWN bit. If it is zero, then this buffer is |
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* not ready to be transmitted yet. Also check the '1111' |
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* mark, and make sure that byte-count is reasonable. |
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*/ |
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if (!(tx_descr[1] & LE_OWN)) |
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return; |
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if ((tx_descr[2] & 0xf000) != 0xf000) |
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return; |
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if (buflen < 12 || buflen > 1900) { |
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fatal("[ le_tx(): buflen = %i ]\n", buflen); |
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return; |
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} |
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|
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debug("[ le_tx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x " |
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"=> addr=0x%06x, len=%i bytes, STP=%i ENP=%i ]\n", d->txp, |
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tx_descr[0], tx_descr[1], tx_descr[2], tx_descr[3], |
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bufaddr, buflen, stp, enp); |
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|
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if (d->tx_packet == NULL && !stp) { |
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fatal("[ le_tx(): !stp but tx_packet == NULL ]\n"); |
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return; |
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} |
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|
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if (d->tx_packet != NULL && stp) { |
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fatal("[ le_tx(): stp but tx_packet != NULL ]\n"); |
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free(d->tx_packet); |
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d->tx_packet = NULL; |
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d->tx_packet_len = 0; |
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} |
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|
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/* Where to write to in the tx_packet: */ |
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cur_packet_offset = d->tx_packet_len; |
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|
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/* Start of a new packet: */ |
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if (stp) { |
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d->tx_packet_len = buflen; |
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d->tx_packet = malloc(buflen); |
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if (d->tx_packet == NULL) { |
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fprintf(stderr, "out of memory (1) in " |
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"le_tx()\n"); |
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exit(1); |
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} |
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} else { |
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d->tx_packet_len += buflen; |
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d->tx_packet = realloc(d->tx_packet, d->tx_packet_len); |
297 |
if (d->tx_packet == NULL) { |
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fprintf(stderr, "out of memory (2) in" |
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" le_tx()\n"); |
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exit(1); |
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} |
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} |
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|
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/* Copy data from SRAM into the tx packet: */ |
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for (i=0; i<buflen; i++) { |
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unsigned char ch; |
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ch = d->sram[(bufaddr + i) & (SRAM_SIZE-1)]; |
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d->tx_packet[cur_packet_offset + i] = ch; |
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} |
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|
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/* |
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* Is this the last buffer in a packet? Then transmit |
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* it, cause an interrupt, and free the memory used by |
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* the packet. |
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*/ |
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if (enp) { |
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net_ethernet_tx(net, d, d->tx_packet, d->tx_packet_len); |
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|
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free(d->tx_packet); |
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d->tx_packet = NULL; |
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d->tx_packet_len = 0; |
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|
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d->reg[0] |= LE_TINT; |
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} |
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|
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/* Clear the OWN bit: */ |
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tx_descr[1] &= ~LE_OWN; |
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|
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/* Write back the descriptor to SRAM: */ |
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le_write_16bit(d, d->tdra + d->txp*8 + 2, tx_descr[1]); |
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le_write_16bit(d, d->tdra + d->txp*8 + 4, tx_descr[2]); |
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le_write_16bit(d, d->tdra + d->txp*8 + 6, tx_descr[3]); |
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|
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/* Go to the next descriptor: */ |
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d->txp ++; |
336 |
if (d->txp >= d->tlen) |
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d->txp = 0; |
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} while (d->txp != start_txp); |
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|
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/* We are here if all descriptors were taken care of. */ |
341 |
fatal("[ le_tx(): all TX descriptors used up? ]\n"); |
342 |
} |
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|
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|
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/* |
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* le_rx(): |
347 |
* |
348 |
* This routine should only be called if RXON is enabled. |
349 |
*/ |
350 |
static void le_rx(struct net *net, struct le_data *d) |
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{ |
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int i, start_rxp = d->rxp; |
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uint16_t rx_descr[4]; |
354 |
uint32_t bufaddr, buflen; |
355 |
|
356 |
do { |
357 |
if (d->rx_packet == NULL) |
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return; |
359 |
|
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/* Load the 8 descriptor bytes: */ |
361 |
rx_descr[0] = le_read_16bit(d, d->rdra + d->rxp*8 + 0); |
362 |
rx_descr[1] = le_read_16bit(d, d->rdra + d->rxp*8 + 2); |
363 |
rx_descr[2] = le_read_16bit(d, d->rdra + d->rxp*8 + 4); |
364 |
rx_descr[3] = le_read_16bit(d, d->rdra + d->rxp*8 + 6); |
365 |
|
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bufaddr = rx_descr[0] + ((rx_descr[1] & 0xff) << 16); |
367 |
buflen = 4096 - (rx_descr[2] & 0xfff); |
368 |
|
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/* |
370 |
* Check the OWN bit. If it is zero, then this buffer is |
371 |
* not ready to receive data yet. Also check the '1111' |
372 |
* mark, and make sure that byte-count is reasonable. |
373 |
*/ |
374 |
if (!(rx_descr[1] & LE_OWN)) |
375 |
return; |
376 |
if ((rx_descr[2] & 0xf000) != 0xf000) |
377 |
return; |
378 |
if (buflen < 12 || buflen > 1900) { |
379 |
fatal("[ le_rx(): buflen = %i ]\n", buflen); |
380 |
return; |
381 |
} |
382 |
|
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debug("[ le_rx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x " |
384 |
"=> addr=0x%06x, len=%i bytes ]\n", d->rxp, |
385 |
rx_descr[0], rx_descr[1], rx_descr[2], rx_descr[3], |
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bufaddr, buflen); |
387 |
|
388 |
/* Copy data from the packet into SRAM: */ |
389 |
for (i=0; i<buflen; i++) { |
390 |
if (d->rx_packet_offset + i >= d->rx_packet_len) |
391 |
break; |
392 |
d->sram[(bufaddr + i) & (SRAM_SIZE-1)] = |
393 |
d->rx_packet[d->rx_packet_offset + i]; |
394 |
} |
395 |
|
396 |
/* Here, i is the number of bytes copied. */ |
397 |
d->rx_packet_offset += i; |
398 |
|
399 |
/* Set the ENP bit if this was the end of a packet: */ |
400 |
if (d->rx_packet_offset >= d->rx_packet_len) { |
401 |
rx_descr[1] |= LE_ENP; |
402 |
|
403 |
/* |
404 |
* NOTE: The Lance documentation that I have read |
405 |
* says _NOTHING_ about the length being 4 more than |
406 |
* the length of the data. You can guess how |
407 |
* surprised I was when I saw the following in |
408 |
* NetBSD (dev/ic/am7990.c): |
409 |
* |
410 |
* lance_read(sc, LE_RBUFADDR(sc, bix), |
411 |
* (int)rmd.rmd3 - 4); |
412 |
*/ |
413 |
rx_descr[3] &= ~0xfff; |
414 |
rx_descr[3] |= d->rx_packet_len + 4; |
415 |
|
416 |
free(d->rx_packet); |
417 |
d->rx_packet = NULL; |
418 |
d->rx_packet_len = 0; |
419 |
d->rx_packet_offset = 0; |
420 |
d->rx_middle_bit = 0; |
421 |
|
422 |
d->reg[0] |= LE_RINT; |
423 |
} |
424 |
|
425 |
/* Set the STP bit if this was the start of a packet: */ |
426 |
if (!d->rx_middle_bit) { |
427 |
rx_descr[1] |= LE_STP; |
428 |
|
429 |
/* Are we continuing on this packet? */ |
430 |
if (d->rx_packet != NULL) |
431 |
d->rx_middle_bit = 1; |
432 |
} |
433 |
|
434 |
/* Clear the OWN bit: */ |
435 |
rx_descr[1] &= ~LE_OWN; |
436 |
|
437 |
/* Write back the descriptor to SRAM: */ |
438 |
le_write_16bit(d, d->rdra + d->rxp*8 + 2, rx_descr[1]); |
439 |
le_write_16bit(d, d->rdra + d->rxp*8 + 4, rx_descr[2]); |
440 |
le_write_16bit(d, d->rdra + d->rxp*8 + 6, rx_descr[3]); |
441 |
|
442 |
/* Go to the next descriptor: */ |
443 |
d->rxp ++; |
444 |
if (d->rxp >= d->rlen) |
445 |
d->rxp = 0; |
446 |
} while (d->rxp != start_rxp); |
447 |
|
448 |
/* We are here if all descriptors were taken care of. */ |
449 |
fatal("[ le_rx(): all RX descriptors used up? ]\n"); |
450 |
} |
451 |
|
452 |
|
453 |
/* |
454 |
* le_register_fix(): |
455 |
*/ |
456 |
static void le_register_fix(struct net *net, struct le_data *d) |
457 |
{ |
458 |
/* Init with new Initialization block, if needed. */ |
459 |
if (d->reg[0] & LE_INIT) |
460 |
le_chip_init(d); |
461 |
|
462 |
#ifdef LE_DEBUG |
463 |
{ |
464 |
static int x = 1234; |
465 |
if (x != d->reg[0]) { |
466 |
debug("[ le reg[0] = 0x%04x ]\n", d->reg[0]); |
467 |
x = d->reg[0]; |
468 |
} |
469 |
} |
470 |
#endif |
471 |
|
472 |
/* |
473 |
* If the receiver is on: |
474 |
* If there is a current rx_packet, try to receive it into the |
475 |
* Lance buffers. Then try to receive any additional packets. |
476 |
*/ |
477 |
if (d->reg[0] & LE_RXON) { |
478 |
do { |
479 |
if (d->rx_packet != NULL) |
480 |
/* Try to receive the packet: */ |
481 |
le_rx(net, d); |
482 |
|
483 |
if (d->rx_packet != NULL) |
484 |
/* If the packet wasn't fully received, |
485 |
then abort for now. */ |
486 |
break; |
487 |
|
488 |
if (d->rx_packet == NULL && |
489 |
net_ethernet_rx_avail(net, d)) |
490 |
net_ethernet_rx(net, d, |
491 |
&d->rx_packet, &d->rx_packet_len); |
492 |
} while (d->rx_packet != NULL); |
493 |
} |
494 |
|
495 |
/* If the transmitter is on, check for outgoing buffers: */ |
496 |
if (d->reg[0] & LE_TXON) |
497 |
le_tx(net, d); |
498 |
|
499 |
/* SERR should be the OR of BABL, CERR, MISS, and MERR: */ |
500 |
d->reg[0] &= ~LE_SERR; |
501 |
if (d->reg[0] & (LE_BABL | LE_CERR | LE_MISS | LE_MERR)) |
502 |
d->reg[0] |= LE_SERR; |
503 |
|
504 |
/* INTR should be the OR of BABL, MISS, MERR, RINT, TINT, IDON: */ |
505 |
d->reg[0] &= ~LE_INTR; |
506 |
if (d->reg[0] & (LE_BABL | LE_MISS | LE_MERR | LE_RINT | |
507 |
LE_TINT | LE_IDON)) |
508 |
d->reg[0] |= LE_INTR; |
509 |
|
510 |
/* The MERR bit clears some bits: */ |
511 |
if (d->reg[0] & LE_MERR) |
512 |
d->reg[0] &= ~(LE_RXON | LE_TXON); |
513 |
|
514 |
/* The STOP bit clears a lot of stuff: */ |
515 |
#if 0 |
516 |
/* According to the LANCE manual: (doesn't work with Ultrix) */ |
517 |
if (d->reg[0] & LE_STOP) |
518 |
d->reg[0] &= ~(LE_SERR | LE_BABL | LE_CERR | LE_MISS | LE_MERR |
519 |
| LE_RINT | LE_TINT | LE_IDON | LE_INTR | LE_INEA |
520 |
| LE_RXON | LE_TXON | LE_TDMD); |
521 |
#else |
522 |
/* Works with Ultrix: */ |
523 |
if (d->reg[0] & LE_STOP) |
524 |
d->reg[0] &= ~(LE_IDON); |
525 |
#endif |
526 |
} |
527 |
|
528 |
|
529 |
/* |
530 |
* dev_le_tick(): |
531 |
*/ |
532 |
void dev_le_tick(struct cpu *cpu, void *extra) |
533 |
{ |
534 |
struct le_data *d = (struct le_data *) extra; |
535 |
|
536 |
le_register_fix(cpu->machine->emul->net, d); |
537 |
|
538 |
if (d->reg[0] & LE_INTR && d->reg[0] & LE_INEA) |
539 |
cpu_interrupt(cpu, d->irq_nr); |
540 |
else |
541 |
cpu_interrupt_ack(cpu, d->irq_nr); |
542 |
} |
543 |
|
544 |
|
545 |
/* |
546 |
* le_register_write(): |
547 |
* |
548 |
* This function is called when the value 'x' is written to register 'r'. |
549 |
*/ |
550 |
void le_register_write(struct le_data *d, int r, uint32_t x) |
551 |
{ |
552 |
switch (r) { |
553 |
case 0: /* CSR0: */ |
554 |
/* Some bits are write-one-to-clear: */ |
555 |
if (x & LE_BABL) |
556 |
d->reg[r] &= ~LE_BABL; |
557 |
if (x & LE_CERR) |
558 |
d->reg[r] &= ~LE_CERR; |
559 |
if (x & LE_MISS) |
560 |
d->reg[r] &= ~LE_MISS; |
561 |
if (x & LE_MERR) |
562 |
d->reg[r] &= ~LE_MERR; |
563 |
if (x & LE_RINT) |
564 |
d->reg[r] &= ~LE_RINT; |
565 |
if (x & LE_TINT) |
566 |
d->reg[r] &= ~LE_TINT; |
567 |
if (x & LE_IDON) |
568 |
d->reg[r] &= ~LE_IDON; |
569 |
|
570 |
/* Some bits are write-only settable, not clearable: */ |
571 |
if (x & LE_TDMD) |
572 |
d->reg[r] |= LE_TDMD; |
573 |
if (x & LE_STRT) { |
574 |
d->reg[r] |= LE_STRT; |
575 |
d->reg[r] &= ~LE_STOP; |
576 |
} |
577 |
if (x & LE_INIT) { |
578 |
if (!(d->reg[r] & LE_STOP)) |
579 |
fatal("[ le: attempt to INIT before" |
580 |
" STOPped! ]\n"); |
581 |
d->reg[r] |= LE_INIT; |
582 |
d->reg[r] &= ~LE_STOP; |
583 |
} |
584 |
if (x & LE_STOP) { |
585 |
d->reg[r] |= LE_STOP; |
586 |
/* STOP takes precedence over STRT and INIT: */ |
587 |
d->reg[r] &= ~(LE_STRT | LE_INIT); |
588 |
} |
589 |
|
590 |
/* Some bits get through, both settable and clearable: */ |
591 |
d->reg[r] &= ~LE_INEA; |
592 |
d->reg[r] |= (x & LE_INEA); |
593 |
break; |
594 |
|
595 |
default: |
596 |
/* CSR1, CSR2, and CSR3: */ |
597 |
d->reg[r] = x; |
598 |
} |
599 |
} |
600 |
|
601 |
|
602 |
/* |
603 |
* dev_le_sram_access(): |
604 |
*/ |
605 |
int dev_le_sram_access(struct cpu *cpu, struct memory *mem, |
606 |
uint64_t relative_addr, unsigned char *data, size_t len, |
607 |
int writeflag, void *extra) |
608 |
{ |
609 |
int i, retval; |
610 |
struct le_data *d = extra; |
611 |
|
612 |
#ifdef LE_DEBUG |
613 |
if (writeflag == MEM_WRITE) { |
614 |
fatal("[ le_sram: write to addr 0x%06x: ", (int)relative_addr); |
615 |
for (i=0; i<len; i++) |
616 |
fatal("%02x ", data[i]); |
617 |
fatal("]\n"); |
618 |
} |
619 |
#endif |
620 |
|
621 |
/* Read/write of the SRAM: */ |
622 |
if (relative_addr < SRAM_SIZE && relative_addr + len <= SRAM_SIZE) { |
623 |
if (writeflag == MEM_READ) { |
624 |
memcpy(data, d->sram + relative_addr, len); |
625 |
if (!quiet_mode) { |
626 |
debug("[ le: read from SRAM offset 0x%05x:", |
627 |
relative_addr); |
628 |
for (i=0; i<len; i++) |
629 |
debug(" %02x", data[i]); |
630 |
debug(" ]\n"); |
631 |
} |
632 |
retval = 9; /* 9 cycles */ |
633 |
} else { |
634 |
memcpy(d->sram + relative_addr, data, len); |
635 |
if (!quiet_mode) { |
636 |
debug("[ le: write to SRAM offset 0x%05x:", |
637 |
relative_addr); |
638 |
for (i=0; i<len; i++) |
639 |
debug(" %02x", data[i]); |
640 |
debug(" ]\n"); |
641 |
} |
642 |
retval = 6; /* 6 cycles */ |
643 |
} |
644 |
return retval; |
645 |
} |
646 |
|
647 |
return 0; |
648 |
} |
649 |
|
650 |
|
651 |
/* |
652 |
* dev_le_access(): |
653 |
*/ |
654 |
int dev_le_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, |
655 |
unsigned char *data, size_t len, int writeflag, void *extra) |
656 |
{ |
657 |
uint64_t idata = 0, odata = 0; |
658 |
int i, retval = 1; |
659 |
struct le_data *d = extra; |
660 |
|
661 |
idata = memory_readmax64(cpu, data, len); |
662 |
|
663 |
#ifdef LE_DEBUG |
664 |
if (writeflag == MEM_WRITE) { |
665 |
fatal("[ le: write to addr 0x%06x: ", (int)relative_addr); |
666 |
for (i=0; i<len; i++) |
667 |
fatal("%02x ", data[i]); |
668 |
fatal("]\n"); |
669 |
} |
670 |
#endif |
671 |
|
672 |
/* Read from station's ROM (ethernet address): */ |
673 |
if (relative_addr >= 0xc0000 && relative_addr <= 0xfffff) { |
674 |
i = (relative_addr & 0xff) / 4; |
675 |
i = d->rom[i & (ROM_SIZE-1)]; |
676 |
|
677 |
if (writeflag == MEM_READ) { |
678 |
odata = (i << 24) + (i << 16) + (i << 8) + i; |
679 |
} else { |
680 |
fatal("[ le: WRITE to ethernet addr (%08lx):", |
681 |
(long)relative_addr); |
682 |
for (i=0; i<len; i++) |
683 |
fatal(" %02x", data[i]); |
684 |
fatal(" ]\n"); |
685 |
} |
686 |
|
687 |
retval = 13; /* 13 cycles */ |
688 |
goto do_return; |
689 |
} |
690 |
|
691 |
|
692 |
switch (relative_addr) { |
693 |
|
694 |
/* Register read/write: */ |
695 |
case 0: |
696 |
if (writeflag==MEM_READ) { |
697 |
odata = d->reg[d->reg_select]; |
698 |
if (!quiet_mode) |
699 |
debug("[ le: read from register 0x%02x: 0x" |
700 |
"%02x ]\n", d->reg_select, (int)odata); |
701 |
/* |
702 |
* A read from csr1..3 should return "undefined" |
703 |
* result if the stop bit is set. However, Ultrix |
704 |
* seems to do just that, so let's _not_ print |
705 |
* a warning here. |
706 |
*/ |
707 |
} else { |
708 |
if (!quiet_mode) |
709 |
debug("[ le: write to register 0x%02x: 0x" |
710 |
"%02x ]\n", d->reg_select, (int)idata); |
711 |
/* |
712 |
* A write to from csr1..3 when the stop bit is |
713 |
* set should be ignored. However, Ultrix writes |
714 |
* even if the stop bit is set, so let's _not_ |
715 |
* print a warning about it. |
716 |
*/ |
717 |
le_register_write(d, d->reg_select, idata); |
718 |
} |
719 |
break; |
720 |
|
721 |
/* Register select: */ |
722 |
case 4: |
723 |
if (writeflag==MEM_READ) { |
724 |
odata = d->reg_select; |
725 |
if (!quiet_mode) |
726 |
debug("[ le: read from register select: " |
727 |
"0x%02x ]\n", (int)odata); |
728 |
} else { |
729 |
if (!quiet_mode) |
730 |
debug("[ le: write to register select: " |
731 |
"0x%02x ]\n", (int)idata); |
732 |
d->reg_select = idata & (N_REGISTERS - 1); |
733 |
if (idata >= N_REGISTERS) |
734 |
fatal("[ le: WARNING! register select %i " |
735 |
"(max is %i) ]\n", idata, N_REGISTERS - 1); |
736 |
} |
737 |
break; |
738 |
|
739 |
default: |
740 |
if (writeflag==MEM_READ) { |
741 |
fatal("[ le: read from UNIMPLEMENTED addr 0x%06x ]\n", |
742 |
(int)relative_addr); |
743 |
} else { |
744 |
fatal("[ le: write to UNIMPLEMENTED addr 0x%06x: " |
745 |
"0x%08x ]\n", (int)relative_addr, (int)idata); |
746 |
} |
747 |
} |
748 |
|
749 |
do_return: |
750 |
if (writeflag == MEM_READ) { |
751 |
memory_writemax64(cpu, data, len, odata); |
752 |
#ifdef LE_DEBUG |
753 |
fatal("[ le: read from addr 0x%06x: 0x%08x ]\n", |
754 |
relative_addr, odata); |
755 |
#endif |
756 |
} |
757 |
|
758 |
dev_le_tick(cpu, extra); |
759 |
|
760 |
return retval; |
761 |
} |
762 |
|
763 |
|
764 |
/* |
765 |
* dev_le_init(): |
766 |
*/ |
767 |
void dev_le_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, |
768 |
uint64_t buf_start, uint64_t buf_end, int irq_nr, int len) |
769 |
{ |
770 |
char *name2; |
771 |
size_t nlen = 55; |
772 |
struct le_data *d = malloc(sizeof(struct le_data)); |
773 |
|
774 |
if (d == NULL) { |
775 |
fprintf(stderr, "out of memory\n"); |
776 |
exit(1); |
777 |
} |
778 |
|
779 |
memset(d, 0, sizeof(struct le_data)); |
780 |
d->irq_nr = irq_nr; |
781 |
|
782 |
d->sram = malloc(SRAM_SIZE); |
783 |
if (d->sram == NULL) { |
784 |
fprintf(stderr, "out of memory\n"); |
785 |
exit(1); |
786 |
} |
787 |
memset(d->sram, 0, SRAM_SIZE); |
788 |
|
789 |
/* TODO: Are these actually used yet? */ |
790 |
d->len = len; |
791 |
d->buf_start = buf_start; |
792 |
d->buf_end = buf_end; |
793 |
|
794 |
/* Initial register contents: */ |
795 |
d->reg[0] = LE_STOP; |
796 |
|
797 |
d->tx_packet = NULL; |
798 |
d->rx_packet = NULL; |
799 |
|
800 |
/* ROM (including the MAC address): */ |
801 |
net_generate_unique_mac(machine, &d->rom[0]); |
802 |
|
803 |
/* |
804 |
* NOTE: According to the Lance documentation, the low order bit of |
805 |
* a physical MAC address should be clear. However, NetBSD and |
806 |
* Linux drop packets if the _first_ byte's lowest bit is not zero. |
807 |
*/ |
808 |
d->rom[0] &= ~1; |
809 |
d->rom[5] &= ~1; |
810 |
|
811 |
/* Copies of the MAC address and a test pattern: */ |
812 |
d->rom[10] = d->rom[21] = d->rom[5]; |
813 |
d->rom[11] = d->rom[20] = d->rom[4]; |
814 |
d->rom[12] = d->rom[19] = d->rom[3]; |
815 |
d->rom[7] = d->rom[8] = d->rom[23] = |
816 |
d->rom[13] = d->rom[18] = d->rom[2]; |
817 |
d->rom[6] = d->rom[9] = d->rom[22] = |
818 |
d->rom[14] = d->rom[17] = d->rom[1]; |
819 |
d->rom[15] = d->rom[16] = d->rom[0]; |
820 |
d->rom[24] = d->rom[28] = 0xff; |
821 |
d->rom[25] = d->rom[29] = 0x00; |
822 |
d->rom[26] = d->rom[30] = 0x55; |
823 |
d->rom[27] = d->rom[31] = 0xaa; |
824 |
|
825 |
memory_device_register(mem, "le_sram", baseaddr, |
826 |
SRAM_SIZE, dev_le_sram_access, (void *)d, |
827 |
MEM_DYNTRANS_OK | MEM_DYNTRANS_WRITE_OK |
828 |
| MEM_READING_HAS_NO_SIDE_EFFECTS, d->sram); |
829 |
|
830 |
name2 = malloc(nlen); |
831 |
if (name2 == NULL) { |
832 |
fprintf(stderr, "out of memory in dev_le_init()\n"); |
833 |
exit(1); |
834 |
} |
835 |
snprintf(name2, nlen, "le [%02x:%02x:%02x:%02x:%02x:%02x]", |
836 |
d->rom[0], d->rom[1], d->rom[2], d->rom[3], d->rom[4], d->rom[5]); |
837 |
|
838 |
memory_device_register(mem, name2, baseaddr + 0x100000, |
839 |
len - 0x100000, dev_le_access, (void *)d, MEM_DEFAULT, NULL); |
840 |
|
841 |
machine_add_tickfunction(machine, dev_le_tick, d, LE_TICK_SHIFT); |
842 |
|
843 |
net_add_nic(machine->emul->net, d, &d->rom[0]); |
844 |
} |
845 |
|