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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_i80321.c,v 1.23 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: Intel i80321 (ARM) core functionality |
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* |
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* o) Interrupt controller |
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* o) Timer |
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* o) PCI controller |
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* o) Memory controller |
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* |
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* TODO: |
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* o) LOTS of things left to implement. |
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* o) This is hardcoded for little endian emulation. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "timer.h" |
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|
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|
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#include "i80321reg.h" |
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|
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#define TICK_SHIFT 15 |
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#define DEV_I80321_LENGTH VERDE_PMMR_SIZE |
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|
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struct i80321_data { |
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/* Interrupt Controller */ |
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struct interrupt irq; |
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uint32_t *status; /* Note: these point to i80321_isrc */ |
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uint32_t *enable; /* and i80321_inten in the CPU! */ |
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|
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/* Timer: */ |
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struct timer *timer; |
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double hz; |
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int pending_tmr0_interrupts; |
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|
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/* PCI Controller: */ |
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uint32_t pci_addr; |
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struct pci_data *pci_bus; |
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|
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/* Memory Controller: */ |
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uint32_t mcu_reg[0x100 / sizeof(uint32_t)]; |
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}; |
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|
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|
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static void i80321_assert(struct i80321_data *d, uint32_t linemask) |
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{ |
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*d->status |= linemask; |
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if (*d->status & *d->enable) |
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INTERRUPT_ASSERT(d->irq); |
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} |
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static void i80321_deassert(struct i80321_data *d, uint32_t linemask) |
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{ |
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*d->status &= ~linemask; |
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if (!(*d->status & *d->enable)) |
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INTERRUPT_DEASSERT(d->irq); |
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} |
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|
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|
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/* |
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* i80321_interrupt_assert(): |
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* i80321_interrupt_deassert(): |
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* |
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* Called whenever an i80321 interrupt is asserted/deasserted. |
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*/ |
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void i80321_interrupt_assert(struct interrupt *interrupt) |
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{ i80321_assert(interrupt->extra, interrupt->line); } |
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void i80321_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct i80321_data *d = interrupt->extra; |
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|
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/* Ack. timer interrupts: */ |
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if (interrupt->line == 1 << 9 && |
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d->pending_tmr0_interrupts > 0) |
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d->pending_tmr0_interrupts --; |
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|
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i80321_deassert(d, interrupt->line); |
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} |
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|
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|
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/* TMR0 ticks, called d->hz times per second. */ |
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static void tmr0_tick(struct timer *t, void *extra) |
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{ |
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struct i80321_data *d = extra; |
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d->pending_tmr0_interrupts ++; |
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} |
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|
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|
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DEVICE_TICK(i80321) |
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{ |
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struct i80321_data *d = extra; |
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|
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if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) { |
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i80321_assert(d, 1 << 9); |
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cpu->cd.arm.tisr |= TISR_TMR0; |
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} else { |
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i80321_deassert(d, 1 << 9); |
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cpu->cd.arm.tisr &= ~TISR_TMR0; |
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} |
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} |
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|
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|
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DEVICE_ACCESS(i80321) |
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{ |
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struct i80321_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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char *n = NULL; |
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int bus, dev, func, reg; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* PCI configuration space: */ |
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if (relative_addr >= 0x100 && relative_addr < 0x140) { |
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/* TODO */ |
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goto ret; |
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} |
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|
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/* MCU registers: */ |
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if (relative_addr >= VERDE_MCU_BASE && |
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relative_addr < VERDE_MCU_BASE + VERDE_MCU_SIZE) { |
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int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t); |
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if (writeflag == MEM_WRITE) |
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d->mcu_reg[regnr] = idata; |
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else |
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odata = d->mcu_reg[regnr]; |
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} |
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|
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|
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switch (relative_addr) { |
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|
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/* Address Translation Unit: */ |
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case VERDE_ATU_BASE + ATU_IALR0: |
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case VERDE_ATU_BASE + ATU_IATVR0: |
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case VERDE_ATU_BASE + ATU_IALR1: |
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case VERDE_ATU_BASE + ATU_IALR2: |
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case VERDE_ATU_BASE + ATU_IATVR2: |
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case VERDE_ATU_BASE + ATU_OIOWTVR: |
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case VERDE_ATU_BASE + ATU_OMWTVR0: |
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case VERDE_ATU_BASE + ATU_OUMWTVR0: |
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case VERDE_ATU_BASE + ATU_OMWTVR1: |
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case VERDE_ATU_BASE + ATU_OUMWTVR1: |
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/* Ignoring these for now. TODO */ |
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break; |
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case VERDE_ATU_BASE + ATU_ATUCR: |
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/* ATU configuration register; ignored for now. TODO */ |
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break; |
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case VERDE_ATU_BASE + ATU_PCSR: |
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/* TODO: Temporary hack to allow NetBSD/evbarm to |
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reboot itself. Should be rewritten as soon as possible! */ |
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if (writeflag == MEM_WRITE && idata == 0x30) { |
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int j; |
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for (j=0; j<cpu->machine->ncpus; j++) |
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cpu->machine->cpus[j]->running = 0; |
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cpu->machine->exit_without_entering_debugger = 1; |
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} |
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break; |
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case VERDE_ATU_BASE + ATU_ATUIMR: |
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case VERDE_ATU_BASE + ATU_IABAR3: |
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case VERDE_ATU_BASE + ATU_IAUBAR3: |
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case VERDE_ATU_BASE + ATU_IALR3: |
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case VERDE_ATU_BASE + ATU_IATVR3: |
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/* Ignoring these for now. TODO */ |
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break; |
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case VERDE_ATU_BASE + ATU_OCCAR: |
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/* PCI address */ |
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if (writeflag == MEM_WRITE) { |
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d->pci_addr = idata; |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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bus = 0; /* NOTE */ |
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bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg); |
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} else { |
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odata = d->pci_addr; |
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} |
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break; |
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case VERDE_ATU_BASE + ATU_OCCDR: |
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case VERDE_ATU_BASE + ATU_OCCDR + 1: |
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case VERDE_ATU_BASE + ATU_OCCDR + 2: |
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case VERDE_ATU_BASE + ATU_OCCDR + 3: |
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/* PCI data */ |
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if (writeflag == MEM_READ) { |
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uint64_t tmp; |
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bus_pci_data_access(cpu, d->pci_bus, &tmp, |
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sizeof(uint32_t), MEM_READ); |
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switch (relative_addr) { |
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case VERDE_ATU_BASE + ATU_OCCDR + 1: |
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odata = tmp >> 8; break; |
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case VERDE_ATU_BASE + ATU_OCCDR + 2: |
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odata = tmp >> 16; break; |
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case VERDE_ATU_BASE + ATU_OCCDR + 3: |
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odata = tmp >> 24; break; |
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default:odata = tmp; |
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} |
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} else { |
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uint64_t tmp; |
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unsigned int i; |
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int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR); |
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bus_pci_data_access(cpu, d->pci_bus, &tmp, |
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sizeof(uint32_t), MEM_READ); |
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for (i=0; i<len; i++) { |
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uint8_t b = idata >> (i*8); |
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tmp &= ~(0xff << ((r+i)*8)); |
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tmp |= b << ((r+i)*8); |
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} |
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tmp &= 0xffffffff; /* needed because << is 32-bit */ |
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bus_pci_data_access(cpu, d->pci_bus, &tmp, |
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sizeof(uint32_t), MEM_WRITE); |
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} |
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break; |
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case VERDE_ATU_BASE + ATU_PCIXSR: |
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odata = 0; /* TODO */ |
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break; |
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|
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/* Memory Controller Unit: */ |
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case VERDE_MCU_BASE + MCU_SDBR: |
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n = "MCU_SDBR"; |
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break; |
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case VERDE_MCU_BASE + MCU_SBR0: |
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n = "MCU_SBR0"; |
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break; |
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case VERDE_MCU_BASE + MCU_SBR1: |
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n = "MCU_SBR1"; |
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break; |
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|
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default:if (writeflag == MEM_READ) { |
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fatal("[ i80321: read from 0x%x ]\n", |
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(int)relative_addr); |
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} else { |
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fatal("[ i80321: write to 0x%x: 0x%llx ]\n", |
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(int)relative_addr, (long long)idata); |
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} |
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} |
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|
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if (n != NULL) { |
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if (writeflag == MEM_READ) { |
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debug("[ i80321: read from %s ]\n", n); |
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} else { |
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debug("[ i80321: write to %s: 0x%llx ]\n", |
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n, (long long)idata); |
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} |
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} |
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|
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ret: |
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(i80321) |
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{ |
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struct i80321_data *d; |
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uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576; |
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uint32_t base; |
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char tmpstr[300]; |
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struct cpu *cpu = devinit->machine->cpus[devinit-> |
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machine->bootstrap_cpu]; |
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int i; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct i80321_data))); |
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memset(d, 0, sizeof(struct i80321_data)); |
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|
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/* Connect to the CPU interrupt pin: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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|
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/* Register 32 i80321 interrupts: */ |
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for (i=0; i<32; i++) { |
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struct interrupt template; |
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char tmpstr[300]; |
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snprintf(tmpstr, sizeof(tmpstr), "%s.i80321.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = tmpstr; |
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template.extra = d; |
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template.interrupt_assert = i80321_interrupt_assert; |
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template.interrupt_deassert = i80321_interrupt_deassert; |
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interrupt_handler_register(&template); |
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|
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/* |
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* Connect the CPU's TMR0 and TMR1 interrupts to these |
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* i80321 timer interrupts (nr 9 and 10): |
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*/ |
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if (i == 9) |
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INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr0_irq); |
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if (i == 10) |
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INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr1_irq); |
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} |
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|
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d->status = &cpu->cd.arm.i80321_isrc; |
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d->enable = &cpu->cd.arm.i80321_inten; |
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|
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d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000; |
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d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25; |
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d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25; |
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|
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snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path); |
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|
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d->pci_bus = bus_pci_init(devinit->machine, |
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tmpstr /* pciirq */, |
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0x90000000 /* TODO: pci_io_offset */, |
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0x90010000 /* TODO: pci_mem_offset */, |
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0xffff0000 /* TODO: pci_portbase */, |
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0x00000000 /* TODO: pci_membase */, |
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tmpstr /* pci_irqbase */, |
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0x90000000 /* TODO: isa_portbase */, |
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0x90010000 /* TODO: isa_membase */, |
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"TODO: isa_irqbase" /* TODO: isa_irqbase */); |
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|
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_I80321_LENGTH, |
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dev_i80321_access, d, DM_DEFAULT, NULL); |
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|
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/* TODO: Don't hardcode to 100 Hz! */ |
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d->hz = 100; |
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d->timer = timer_add(d->hz, tmr0_tick, d); |
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|
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machine_add_tickfunction(devinit->machine, dev_i80321_tick, |
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d, TICK_SHIFT); |
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|
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devinit->return_ptr = d->pci_bus; |
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|
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return 1; |
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} |
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|