src/devices/dev_dreamcast_asic.c

/*
 *  Copyright (C) 2006-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_dreamcast_asic.c,v 1.9 2007/06/15 18:44:19 debug Exp $
 *  
 *  COMMENT: Dreamcast-specific ASIC
 *
 *  A simple device which forwards various Dreamcast device events as
 *  interrupts 13, 11, or 9, to the CPU.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>

#include "cpu.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "dreamcast_sysasicvar.h"
#include "sh4_exception.h"


#define debug fatal

#define DREAMCAST_ASIC_TICK_SHIFT       15

struct dreamcast_asic_data {
        uint32_t        pending_irq[3];
        uint32_t        mask_13[3];
        uint32_t        mask_11[3];
        uint32_t        mask_9[3];

        int             asserted_13;
        int             asserted_11;
        int             asserted_9;

        struct interrupt irq_13;
        struct interrupt irq_11;
        struct interrupt irq_9;
};


DEVICE_TICK(dreamcast_asic)
{
        struct dreamcast_asic_data *d = extra;
        int i, old_asserted_13 = d->asserted_13, old_asserted_11 =
            d->asserted_11, old_asserted_9 = d->asserted_9;

        d->asserted_13 = d->asserted_11 = d->asserted_9 = 0;

        for (i=0; i<3; i++) {
                if (d->pending_irq[i] & d->mask_13[i])
                        d->asserted_13 = 1;

                if (d->pending_irq[i] & d->mask_11[i])
                        d->asserted_11 = 1;

                if (d->pending_irq[i] & d->mask_9[i])
                        d->asserted_9 = 1;
        }

        if (d->asserted_13 != old_asserted_13) {
                if (d->asserted_13)
                        INTERRUPT_ASSERT(d->irq_13);
                else
                        INTERRUPT_DEASSERT(d->irq_13);
        }
        if (d->asserted_11 != old_asserted_11) {
                if (d->asserted_11)
                        INTERRUPT_ASSERT(d->irq_11);
                else
                        INTERRUPT_DEASSERT(d->irq_11);
        }
        if (d->asserted_9 != old_asserted_9) {
                if (d->asserted_9)
                        INTERRUPT_ASSERT(d->irq_9);
                else
                        INTERRUPT_DEASSERT(d->irq_9);
        }
}


DEVICE_ACCESS(dreamcast_asic)
{
        struct dreamcast_asic_data *d = extra;
        uint64_t idata = 0, odata = 0;
        int r;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        r = (relative_addr / 4) & 3;
        if (r == 3) {
                fatal("[ dreamcast_asic: Bad address ]\n");
                r = 0;
        }

        switch (relative_addr) {

        case 0:
        case 4:
        case 8: if (writeflag == MEM_READ) {
                        odata = d->pending_irq[r];
                } else {
                        /*  Should only be used interally by GXemul:  */
                        if (idata & 0x100000000ULL) {
                                /*  Set specific bits:  */
                                d->pending_irq[r] |= idata;
                        } else {
                                /*  Clear interrupt assertions:  */
                                d->pending_irq[r] &= ~idata;
                        }
                        dev_dreamcast_asic_tick(cpu, d);
                }
                break;

        case 0x10:
        case 0x14:
        case 0x18:
                if (writeflag == MEM_WRITE) {
                        d->mask_13[r] = idata;
                        dev_dreamcast_asic_tick(cpu, d);
                } else {
                        odata = d->mask_13[r];
                }
                break;

        case 0x20:
        case 0x24:
        case 0x28:
                if (writeflag == MEM_WRITE) {
                        d->mask_11[r] = idata;
                        dev_dreamcast_asic_tick(cpu, d);
                } else {
                        odata = d->mask_11[r];
                }
                break;

        case 0x30:
        case 0x34:
        case 0x38:
                if (writeflag == MEM_WRITE) {
                        d->mask_9[r] = idata;
                        dev_dreamcast_asic_tick(cpu, d);
                } else {
                        odata = d->mask_9[r];
                }
                break;

        default:if (writeflag == MEM_READ) {
                        fatal("[ dreamcast_asic: read from addr 0x%x ]\n",
                            (int)relative_addr);
                } else {
                        fatal("[ dreamcast_asic: write to addr 0x%x: 0x%x ]\n",
                            (int)relative_addr, (int)idata);
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(dreamcast_asic)
{
        char tmpstr[300];
        struct machine *machine = devinit->machine;
        struct dreamcast_asic_data *d;

        CHECK_ALLOCATION(d = malloc(sizeof(struct dreamcast_asic_data)));
        memset(d, 0, sizeof(struct dreamcast_asic_data));

        /*  Connect to SH4 interrupt levels 13, 11, and 9:  */
        snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
            devinit->interrupt_path, SH_INTEVT_IRL13);
        INTERRUPT_CONNECT(tmpstr, d->irq_13);
        snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
            devinit->interrupt_path, SH_INTEVT_IRL11);
        INTERRUPT_CONNECT(tmpstr, d->irq_11);
        snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
            devinit->interrupt_path, SH_INTEVT_IRL9);
        INTERRUPT_CONNECT(tmpstr, d->irq_9);

        memory_device_register(machine->memory, devinit->name, SYSASIC_BASE,
            SYSASIC_SIZE, dev_dreamcast_asic_access, d, DM_DEFAULT, NULL);

        machine_add_tickfunction(devinit->machine, dev_dreamcast_asic_tick, d,
            DREAMCAST_ASIC_TICK_SHIFT);

        return 1;
}

1	dpavlin	32	/*
2	dpavlin	34	* Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3	dpavlin	32	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	42	* $Id: dev_dreamcast_asic.c,v 1.9 2007/06/15 18:44:19 debug Exp $
29	dpavlin	32	*
30	dpavlin	42	* COMMENT: Dreamcast-specific ASIC
31	dpavlin	32	*
32			* A simple device which forwards various Dreamcast device events as
33			* interrupts 13, 11, or 9, to the CPU.
34			*/
35
36			#include <stdio.h>
37			#include <stdlib.h>
38			#include <string.h>
39			#include <sys/time.h>
40
41			#include "cpu.h"
42			#include "device.h"
43			#include "machine.h"
44			#include "memory.h"
45			#include "misc.h"
46
47			#include "dreamcast_sysasicvar.h"
48			#include "sh4_exception.h"
49
50
51			#define debug fatal
52
53			#define DREAMCAST_ASIC_TICK_SHIFT 15
54
55			struct dreamcast_asic_data {
56			uint32_t pending_irq[3];
57			uint32_t mask_13[3];
58			uint32_t mask_11[3];
59			uint32_t mask_9[3];
60
61			int asserted_13;
62			int asserted_11;
63			int asserted_9;
64	dpavlin	34
65			struct interrupt irq_13;
66			struct interrupt irq_11;
67			struct interrupt irq_9;
68	dpavlin	32	};
69
70
71			DEVICE_TICK(dreamcast_asic)
72			{
73	dpavlin	42	struct dreamcast_asic_data *d = extra;
74	dpavlin	32	int i, old_asserted_13 = d->asserted_13, old_asserted_11 =
75			d->asserted_11, old_asserted_9 = d->asserted_9;
76
77			d->asserted_13 = d->asserted_11 = d->asserted_9 = 0;
78
79			for (i=0; i<3; i++) {
80			if (d->pending_irq[i] & d->mask_13[i])
81			d->asserted_13 = 1;
82
83			if (d->pending_irq[i] & d->mask_11[i])
84			d->asserted_11 = 1;
85
86			if (d->pending_irq[i] & d->mask_9[i])
87			d->asserted_9 = 1;
88			}
89
90			if (d->asserted_13 != old_asserted_13) {
91			if (d->asserted_13)
92	dpavlin	34	INTERRUPT_ASSERT(d->irq_13);
93	dpavlin	32	else
94	dpavlin	34	INTERRUPT_DEASSERT(d->irq_13);
95	dpavlin	32	}
96			if (d->asserted_11 != old_asserted_11) {
97			if (d->asserted_11)
98	dpavlin	34	INTERRUPT_ASSERT(d->irq_11);
99	dpavlin	32	else
100	dpavlin	34	INTERRUPT_DEASSERT(d->irq_11);
101	dpavlin	32	}
102			if (d->asserted_9 != old_asserted_9) {
103			if (d->asserted_9)
104	dpavlin	34	INTERRUPT_ASSERT(d->irq_9);
105	dpavlin	32	else
106	dpavlin	34	INTERRUPT_DEASSERT(d->irq_9);
107	dpavlin	32	}
108			}
109
110
111			DEVICE_ACCESS(dreamcast_asic)
112			{
113	dpavlin	42	struct dreamcast_asic_data *d = extra;
114	dpavlin	32	uint64_t idata = 0, odata = 0;
115			int r;
116
117			if (writeflag == MEM_WRITE)
118			idata = memory_readmax64(cpu, data, len);
119
120			r = (relative_addr / 4) & 3;
121			if (r == 3) {
122			fatal("[ dreamcast_asic: Bad address ]\n");
123			r = 0;
124			}
125
126			switch (relative_addr) {
127
128			case 0:
129			case 4:
130			case 8: if (writeflag == MEM_READ) {
131			odata = d->pending_irq[r];
132			} else {
133			/* Should only be used interally by GXemul: */
134			if (idata & 0x100000000ULL) {
135			/* Set specific bits: */
136			d->pending_irq[r] \|= idata;
137			} else {
138			/* Clear interrupt assertions: */
139			d->pending_irq[r] &= ~idata;
140			}
141			dev_dreamcast_asic_tick(cpu, d);
142			}
143			break;
144
145			case 0x10:
146			case 0x14:
147			case 0x18:
148			if (writeflag == MEM_WRITE) {
149			d->mask_13[r] = idata;
150			dev_dreamcast_asic_tick(cpu, d);
151			} else {
152			odata = d->mask_13[r];
153			}
154			break;
155
156			case 0x20:
157			case 0x24:
158			case 0x28:
159			if (writeflag == MEM_WRITE) {
160			d->mask_11[r] = idata;
161			dev_dreamcast_asic_tick(cpu, d);
162			} else {
163			odata = d->mask_11[r];
164			}
165			break;
166
167			case 0x30:
168			case 0x34:
169			case 0x38:
170			if (writeflag == MEM_WRITE) {
171			d->mask_9[r] = idata;
172			dev_dreamcast_asic_tick(cpu, d);
173			} else {
174			odata = d->mask_9[r];
175			}
176			break;
177
178			default:if (writeflag == MEM_READ) {
179			fatal("[ dreamcast_asic: read from addr 0x%x ]\n",
180			(int)relative_addr);
181			} else {
182			fatal("[ dreamcast_asic: write to addr 0x%x: 0x%x ]\n",
183			(int)relative_addr, (int)idata);
184			}
185			}
186
187			if (writeflag == MEM_READ)
188			memory_writemax64(cpu, data, len, odata);
189
190			return 1;
191			}
192
193
194			DEVINIT(dreamcast_asic)
195			{
196	dpavlin	34	char tmpstr[300];
197	dpavlin	32	struct machine *machine = devinit->machine;
198	dpavlin	42	struct dreamcast_asic_data *d;
199	dpavlin	34
200	dpavlin	42	CHECK_ALLOCATION(d = malloc(sizeof(struct dreamcast_asic_data)));
201	dpavlin	32	memset(d, 0, sizeof(struct dreamcast_asic_data));
202
203	dpavlin	34	/* Connect to SH4 interrupt levels 13, 11, and 9: */
204			snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
205			devinit->interrupt_path, SH_INTEVT_IRL13);
206			INTERRUPT_CONNECT(tmpstr, d->irq_13);
207			snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
208			devinit->interrupt_path, SH_INTEVT_IRL11);
209			INTERRUPT_CONNECT(tmpstr, d->irq_11);
210			snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]",
211			devinit->interrupt_path, SH_INTEVT_IRL9);
212			INTERRUPT_CONNECT(tmpstr, d->irq_9);
213
214	dpavlin	32	memory_device_register(machine->memory, devinit->name, SYSASIC_BASE,
215			SYSASIC_SIZE, dev_dreamcast_asic_access, d, DM_DEFAULT, NULL);
216
217			machine_add_tickfunction(devinit->machine, dev_dreamcast_asic_tick, d,
218	dpavlin	42	DREAMCAST_ASIC_TICK_SHIFT);
219	dpavlin	32
220			return 1;
221			}
222