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++ trunk/HISTORY (local) $Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $ 20051031 Adding disassembly support for more ARM instructions (clz, smul* etc), and adding a hack to support "new tiny" pages for StrongARM. 20051101 Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD 3.7 -> 3.8, and lots of testing). Changing from 1-sector PIO mode 0 transfers to 128-sector PIO mode 3 (in dev_wdc). Various minor ARM dyntrans updates (pc-relative loads from within the same page as the instruction are now treated as constant "mov"). 20051102 Re-enabling instruction combinations (they were accidentally disabled). Dyntrans TLB entries are now overwritten using a round-robin scheme instead of randomly. This increases performance. Fixing a typo in file.c (thanks to Chuan-Hua Chang for noticing it). Experimenting with adding ATAPI support to dev_wdc (to make emulated *BSD detect cdroms as cdroms, not harddisks). 20051104 Various minor updates. 20051105 Continuing on the ATAPI emulation. Seems to work well enough for a NetBSD/cats installation, but not OpenBSD/cats. Various other updates. 20051106 Modifying the -Y command line option to allow scaleup with certain graphic controllers (only dev_vga so far), not just scaledown. Some minor dyntrans cleanups. 20051107 Beginning a cleanup up the PCI subsystem (removing the read_register hack, etc). 20051108 Continuing the cleanup; splitting up some pci devices into a normal autodev device and some separate pci glue code. 20051109 Continuing on the PCI bus stuff; all old pci_*.c have been incorporated into normal devices and/or rewritten as glue code only, adding a dummy Intel 82371AB PIIX4 for Malta (not really tested yet). Minor pckbc fix so that Linux doesn't complain. Working on the DEC 21143 NIC (ethernet mac rom stuff mostly). Various other minor fixes. 20051110 Some more ARM dyntrans fine-tuning (e.g. some instruction combinations (cmps followed by conditional branch within the same page) and special cases for DPIs with regform when the shifter isn't used). 20051111 ARM dyntrans updates: O(n)->O(1) for just-mark-as-non- writable in the generic pc_to_pointers function, and some other minor hacks. Merging Cobalt and evbmips (Malta) ISA interrupt handling, and some minor fixes to allow Linux to accept harddisk irqs. 20051112 Minor device updates (pckbc, dec21143, lpt, ...), most importantly fixing the ALI M1543/M5229 so that harddisk irqs work with Linux/CATS. 20051113 Some more generalizations of the PCI subsystem. Finally took the time to add a hack for SCSI CDROM TOCs; this enables OpenBSD to use partition 'a' (as needed by the OpenBSD installer), and Windows NT's installer to get a bit further. Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs. Continuing on the DEC 21143. 20051114 Minor ARM dyntrans tweaks; ARM cmps+branch optimization when comparing with 0, and generalizing the xchg instr. comb. Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}. 20051115 Continuing on various PPC things (BATs, other address trans- lation things, various loads/stores, BeBox emulation, etc.). Beginning to work on PPC interrupt/exception support. 20051116 Factoring out some code which initializes legacy ISA devices from those machines that use them (bus_isa). Continuing on PPC interrupt/exception support. 20051117 Minor Malta fixes: RTC year offset = 80, disabling a speed hack which caused NetBSD to detect a too fast cpu, and adding a new hack to make Linux detect a faster cpu. Continuing on the Artesyn PM/PPC emulation mode. Adding an Algor emulation skeleton (P4032 and P5064); implementing some of the basics. Continuing on PPC emulation in general; usage of unimplemented SPRs is now easier to track, continuing on memory/exception related issues, etc. 20051118 More work on PPC emulation (tgpr0..3, exception handling, memory stuff, syscalls, etc.). 20051119 Changing the ARM dyntrans code to mostly use cpu->pc, and not necessarily use arm reg 15. Seems to work. Various PPC updates; continuing on the PReP emulation mode. 20051120 Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep to detect the clock. 20051121 More cleanup of the PCI bus (memory and I/O bases, etc). Continuing on various PPC things (decrementer and timebase, WDCs on obio (on PReP) use irq 13, not 14/15). 20051122 Continuing on the CPC700 controller (interrupts etc) for PMPPC, and on PPC stuff in general. Finally! After some bug fixes to the virtual to physical addr translation, NetBSD/{prep,pmppc} 2.1 reach userland and are stable enough to be interacted with. More PCI updates; reverse-endian device access for PowerPC etc. 20051123 Generalizing the IEEE floating point subsystem (moving it out from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c). Input via slave xterms was sometimes not really working; fixing this for ns16550, and a warning message is now displayed if multiple non-xterm consoles are active. Adding some PPC floating point support, etc. Various interrupt related updates (dev_wdc, _ns16550, _8259, and the isa32 common code in machine.c). NetBSD/prep can now be installed! :-) (Well, with some manual commands necessary before running sysinst.) Updating the documentation and various other things to reflect this. 20051124 Various minor documentation updates. Continuing the work on the DEC 21143 NIC. 20051125 LOTS of work on the 21143. Both OpenBSD and NetBSD work fine with it now, except that OpenBSD sometimes gives a time-out warning. Minor documentation updates. ============== RELEASE 0.3.7 ==============
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $ 20051011 Passing -A as the default boot arg for CATS (works fine with OpenBSD/cats). 20051012 Fixing the VGA cursor offset bug, and speeding up framebuffer redraws if character cells contain the same thing as during the last redraw. 20051013 Adding a slow strd ARM instruction hack. 20051017 Minor updates: Adding a dummy i80321 Verde controller (for XScale emulation), fixing the disassembly of the ARM "ldrd" instruction, adding "support" for less-than-4KB pages for ARM (by not adding them to translation tables). 20051020 Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints some boot messages on an emulated Jornada 720. Making dev_ram work better with dyntrans (speeds up some things quite a bit). 20051021 Automatically generating some of the most common ARM load/store multiple instructions. 20051022 Better statistics gathering for the ARM load/store multiple. Various other dyntrans and device updates. 20051023 Various minor updates. 20051024 Continuing; minor device and dyntrans fine-tuning. Adding the first "reasonable" instruction combination hacks for ARM (the cores of NetBSD/cats' memset and memcpy). 20051025 Fixing a dyntrans-related bug in dev_vga. Also changing the dyntrans low/high access notification to only be updated on writes, not reads. Hopefully it will be enough. (dev_vga in charcell mode now seems to work correctly with both reads and writes.) Experimenting with gathering dyntrans statistics (which parts of emulated RAM that are actually executed), and adding instruction combination hacks for cache cleaning and a part of NetBSD's scanc() function. 20051026 Adding a bitmap for ARM emulation which indicates if a page is (specifically) user accessible; loads and stores with the t- flag set can now use the translation arrays, which results in a measurable speedup. 20051027 Dyntrans updates; adding an extra bitmap array for 32-bit emulation modes, speeding up the check whether a physical page has any code translations or not (O(n) -> O(1)). Doing a similar reduction of O(n) to O(1) by avoiding the scan through the translation entries on a translation update (32-bit mode only). Various other minor hacks. 20051029 Quick release, without any testing at all. ============== RELEASE 0.3.6.2 ==============
++ trunk/HISTORY (local) $Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $ 20050628 Continuing the work on the ARM translation engine. end_of_page works. Experimenting with load/store translation caches (virtual -> physical -> host). 20050629 More ARM stuff (memory access translation cache, mostly). This might break a lot of stuff elsewhere, probably some MIPS- related translation things. 20050630 Many load/stores are now automatically generated and included into cpu_arm_instr.c; 1024 functions in total (!). Fixes based on feedback from Alec Voropay: only print 8 hex digits instead of 16 in some cases when emulating 32-bit machines; similar 8 vs 16 digit fix for breakpoint addresses; 4Kc has 16 TLB entries, not 48; the MIPS config select1 register is now printed with "reg ,0". Also changing many other occurances of 16 vs 8 digit output. Adding cache associativity fields to mips_cpu_types.h; updating some other cache fields; making the output of mips_cpu_dumpinfo() look nicer. Generalizing the bintrans stuff for device accesses to also work with the new translation system. (This might also break some MIPS things.) Adding multi-load/store instructions to the ARM disassembler and the translator, and some optimizations of various kinds. 20050701 Adding a simple dev_disk (it can read/write sectors from disk images). 20050712 Adding dev_ether (a simple ethernet send/receive device). Debugger command "ninstrs" for toggling show_nr_of_instructions during runtime. Removing the framebuffer logo. 20050713 Continuing on dev_ether. Adding a dummy cpu_alpha (again). 20050714 More work on cpu_alpha. 20050715 More work on cpu_alpha. Many instructions work, enough to run a simple framebuffer fill test (similar to the ARM test). 20050716 More Alpha stuff. 20050717 Minor updates (Alpha stuff). 20050718 Minor updates (Alpha stuff). 20050719 Generalizing some Alpha instructions. 20050720 More Alpha-related updates. 20050721 Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha. 20050722 Alpha-related updates: userland stuff (Hello World using write() compiled statically for FreeBSD/Alpha runs fine), and more instructions are now implemented. 20050723 Fixing ldq_u and stq_u. Adding more instructions (conditional moves, masks, extracts, shifts). 20050724 More FreeBSD/Alpha userland stuff, and adding some more instructions (inserts). 20050725 Continuing on the Alpha stuff. (Adding dummy ldt/stt.) Adding a -A command line option to turn off alignment checks in some cases (for translated code). Trying to remove the old bintrans code which updated the pc and nr_of_executed_instructions for every instruction. 20050726 Making another attempt att removing the pc/nr of instructions code. This time it worked, huge performance increase for artificial test code, but performance loss for real-world code :-( so I'm scrapping that code for now. Tiny performance increase on Alpha (by using ret instead of jmp, to play nice with the Alpha's branch prediction) for the old MIPS bintrans backend. 20050727 Various minor fixes and cleanups. 20050728 Switching from a 2-level virtual to host/physical translation system for ARM emulation, to a 1-level translation. Trying to switch from 2-level to 1-level for the MIPS bintrans system as well (Alpha only, so far), but there is at least one problem: caches and/or how they work with device mappings. 20050730 Doing the 2-level to 1-level conversion for the i386 backend. The cache/device bug is still there for R2K/3K :( Various other minor updates (Malta etc). The mc146818 clock now updates the UIP bit in a way which works better with Linux for at least sgimips and Malta emulation. Beginning the work on refactoring the dyntrans system. 20050731 Continuing the dyntrans refactoring. Fixing a small but serious host alignment bug in memory_rw. Adding support for big-endian load/stores to the i386 bintrans backend. Another minor i386 bintrans backend update: stores from the zero register are now one (or two) loads shorter. The slt and sltu instructions were incorrectly implemented for the i386 backend; only using them for 32-bit mode for now. 20050801 Continuing the dyntrans refactoring. Cleanup of the ns16550 serial controller (removing unnecessary code). Bugfix (memory corruption bug) in dev_gt, and a patch/hack from Alec Voropay for Linux/Malta. 20050802 More cleanup/refactoring of the dyntrans subsystem: adding phys_page pointers to the lookup tables, for quick jumps between translated pages. Better fix for the ns16550 device (but still no real FIFO functionality). Converting cpu_ppc to the new dyntrans system. This means that I will have to start from scratch with implementing each instruction, and figure out how to implement dual 64/32-bit modes etc. Removing the URISC CPU family, because it was useless. 20050803 When selecting a machine type, the main type can now be omitted if the subtype name is unique. (I.e. -E can be omitted.) Fixing a dyntrans/device update bug. (Writes to offset 0 of a device could sometimes go unnoticed.) Adding an experimental "instruction combination" hack for ARM for memset-like byte fill loops. 20050804 Minor progress on cpu_alpha and related things. Finally fixing the MIPS dmult/dmultu bugs. Fixing some minor TODOs. 20050805 Generalizing the 8259 PIC. It now also works with Cobalt and evbmips emulation, in addition to the x86 hack. Finally converting the ns16550 device to use devinit. Continuing the work on the dyntrans system. Thinking about how to add breakpoints. 20050806 More dyntrans updates. Breakpoints seem to work now. 20050807 Minor updates: cpu_alpha and related things; removing dev_malta (as it isn't used any more). Dyntrans: working on general "show trace tree" support. The trace tree stuff now works with both the old MIPS code and with newer dyntrans modes. :) Continuing on Alpha-related stuff (trying to get *BSD to boot a bit further, adding more instructions, etc). 20050808 Adding a dummy IA64 cpu family, and continuing the refactoring of the dyntrans system. Removing the regression test stuff, because it was more or less useless. Adding loadlinked/storeconditional type instructions to the Alpha emulation. (Needed for Linux/alpha. Not very well tested yet.) 20050809 The function call trace tree now prints a per-function nr of arguments. (Semi-meaningless, since that data isn't read yet from the ELFs; some hardcoded symbols such as memcpy() and strlen() work fine, though.) More dyntrans refactoring; taking out more of the things that are common to all cpu families. 20050810 Working on adding support for "dual mode" for PPC dyntrans (i.e. both 64-bit and 32-bit modes). (Re)adding some simple PPC instructions. 20050811 Adding a dummy M68K cpu family. The dyntrans system isn't ready for variable-length ISAs yet, so it's completely bogus so far. Re-adding more PPC instructions. Adding a hack to src/file.c which allows OpenBSD/mac68k a.out kernels to be loaded. Beginning to add PPC loads/stores. So far they only work in 32-bit mode. 20050812 The configure file option "add_remote" now accepts symbolic host names, in addition to numeric IPv4 addresses. Re-adding more PPC instructions. 20050814 Continuing to port back more PPC instructions. Found and fixed the cache/device write-update bug for 32-bit MIPS bintrans. :-) Triggered a really weird and annoying bug in Compaq's C compiler; ccc sometimes outputs code which loads from an address _before_ checking whether the pointer was NULL or not. (I'm not sure how to handle this problem.) 20050815 Removing all of the old x86 instruction execution code; adding a new (dummy) dyntrans module for x86. Taking the first steps to extend the dyntrans system to support variable-length instructions. Slowly preparing for the next release. 20050816 Adding a dummy SPARC cpu module. Minor updates (documentation etc) for the release. ============== RELEASE 0.3.5 ==============
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