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/* |
/* |
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* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_dec_ioasic.c,v 1.15 2006/01/01 13:17:16 debug Exp $ |
* $Id: dev_dec_ioasic.c,v 1.18 2007/06/15 18:44:19 debug Exp $ |
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* |
* |
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* DECstation "3MIN" and "3MAX" IOASIC device. |
* COMMENT: IOASIC device used in the DECstation "3MIN" and "3MAX" machines |
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* |
* |
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* TODO: Lots of stuff, such as DMA and all bits in the control registers. |
* TODO: Lots of stuff, such as DMA and all bits in the control registers. |
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*/ |
*/ |
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#define IOASIC_DEBUG |
#define IOASIC_DEBUG |
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/* #define debug fatal */ |
/* #define debug fatal */ |
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/* |
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* dev_dec_ioasic_access(): |
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*/ |
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DEVICE_ACCESS(dec_ioasic) |
DEVICE_ACCESS(dec_ioasic) |
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{ |
{ |
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struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra; |
struct dec_ioasic_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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uint64_t curptr; |
uint64_t curptr; |
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int dma_len, dma_res; |
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uint32_t csr; |
uint32_t csr; |
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int regnr; |
int dma_len, dma_res, regnr; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
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/* Make sure that the CPU interrupt is deasserted as |
/* Make sure that the CPU interrupt is deasserted as |
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well: */ |
well: */ |
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if (idata != 0) |
fatal("TODO: interrupt rewrite!\n"); |
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cpu_interrupt_ack(cpu, 8 + idata); |
abort(); |
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// if (idata != 0) |
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// cpu_interrupt_ack(cpu, 8 + idata); |
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} |
} |
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break; |
break; |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] = |
d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] = |
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idata; |
idata; |
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cpu_interrupt_ack(cpu, 8 + 0); |
fatal("TODO: interrupt rewrite!\n"); |
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abort(); |
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// cpu_interrupt_ack(cpu, 8 + 0); |
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} else |
} else |
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odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / |
odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / |
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0x10]; |
0x10]; |
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struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu, |
struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu, |
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struct memory *mem, uint64_t baseaddr, int rackmount_flag) |
struct memory *mem, uint64_t baseaddr, int rackmount_flag) |
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{ |
{ |
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struct dec_ioasic_data *d = malloc(sizeof(struct dec_ioasic_data)); |
struct dec_ioasic_data *d; |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
CHECK_ALLOCATION(d = malloc(sizeof(struct dec_ioasic_data))); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct dec_ioasic_data)); |
memset(d, 0, sizeof(struct dec_ioasic_data)); |
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d->rackmount_flag = rackmount_flag; |
d->rackmount_flag = rackmount_flag; |
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memory_device_register(mem, "dec_ioasic", baseaddr, |
memory_device_register(mem, "dec_ioasic", baseaddr, |
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DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d, |
DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d, |
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DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
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return d; |
return d; |
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} |
} |
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