1 |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
6 |
* |
7 |
* 1. Redistributions of source code must retain the above copyright |
8 |
* notice, this list of conditions and the following disclaimer. |
9 |
* 2. Redistributions in binary form must reproduce the above copyright |
10 |
* notice, this list of conditions and the following disclaimer in the |
11 |
* documentation and/or other materials provided with the distribution. |
12 |
* 3. The name of the author may not be used to endorse or promote products |
13 |
* derived from this software without specific prior written permission. |
14 |
* |
15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
26 |
* |
27 |
* |
28 |
* $Id: dev_algor.c,v 1.3 2006/08/14 17:45:47 debug Exp $ |
29 |
* |
30 |
* Algor misc. stuff. |
31 |
* |
32 |
* TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc. |
33 |
* |
34 |
* CPU irq 2 = ISA, 3 = PCI, 4 = Local. |
35 |
*/ |
36 |
|
37 |
#include <stdio.h> |
38 |
#include <stdlib.h> |
39 |
#include <string.h> |
40 |
|
41 |
#include "cpu.h" |
42 |
#include "device.h" |
43 |
#include "devices.h" |
44 |
#include "machine.h" |
45 |
#include "memory.h" |
46 |
#include "misc.h" |
47 |
|
48 |
#include "algor_p5064reg.h" |
49 |
|
50 |
|
51 |
DEVICE_ACCESS(algor) |
52 |
{ |
53 |
struct algor_data *d = extra; |
54 |
uint64_t idata = 0, odata = 0; |
55 |
char *n = NULL; |
56 |
|
57 |
if (writeflag == MEM_WRITE) |
58 |
idata = memory_readmax64(cpu, data, len); |
59 |
|
60 |
relative_addr += d->base_addr; |
61 |
|
62 |
switch (relative_addr) { |
63 |
|
64 |
case P5064_LED1 + 0x0: |
65 |
case P5064_LED1 + 0x4: |
66 |
case P5064_LED1 + 0x8: |
67 |
case P5064_LED1 + 0xc: |
68 |
break; |
69 |
|
70 |
case P5064_LOCINT: |
71 |
/* |
72 |
* TODO: See how ISAINT is implemented. |
73 |
* |
74 |
* Implemented so far: COM1 only. |
75 |
*/ |
76 |
n = "P5064_LOCINT"; |
77 |
if (writeflag == MEM_READ) { |
78 |
/* Ugly hack for NetBSD startup. TODO: fix */ |
79 |
static int x = 0; |
80 |
if (((++ x) & 0xffff) == 0) |
81 |
odata |= LOCINT_RTC; |
82 |
|
83 |
if (cpu->machine->isa_pic_data.pic1->irr & |
84 |
~cpu->machine->isa_pic_data.pic1->ier & 0x10) |
85 |
odata |= LOCINT_COM1; |
86 |
if (cpu->machine->isa_pic_data.pic1->irr & |
87 |
~cpu->machine->isa_pic_data.pic1->ier & 0x08) |
88 |
odata |= LOCINT_COM2; |
89 |
|
90 |
/* Read => ack: */ |
91 |
cpu->machine->isa_pic_data.pic1->irr &= ~0x18; |
92 |
cpu_interrupt_ack(cpu, 4); |
93 |
} else { |
94 |
if (idata & LOCINT_COM1) |
95 |
cpu->machine->isa_pic_data.pic1->ier &= ~0x10; |
96 |
else |
97 |
cpu->machine->isa_pic_data.pic1->ier |= 0x10; |
98 |
if (idata & LOCINT_COM2) |
99 |
cpu->machine->isa_pic_data.pic1->ier &= ~0x08; |
100 |
else |
101 |
cpu->machine->isa_pic_data.pic1->ier |= 0x08; |
102 |
} |
103 |
break; |
104 |
|
105 |
case P5064_PANIC: |
106 |
n = "P5064_PANIC"; |
107 |
if (writeflag == MEM_READ) |
108 |
odata = 0; |
109 |
break; |
110 |
|
111 |
case P5064_PCIINT: |
112 |
/* |
113 |
* TODO: See how ISAINT is implemented. |
114 |
*/ |
115 |
n = "P5064_PCIINT"; |
116 |
if (writeflag == MEM_READ) { |
117 |
odata = 0; |
118 |
cpu_interrupt_ack(cpu, 3); |
119 |
} |
120 |
break; |
121 |
|
122 |
case P5064_ISAINT: |
123 |
/* |
124 |
* ISA interrupts: |
125 |
* |
126 |
* Bit: IRQ Source: |
127 |
* 0 ISAINT_ISABR |
128 |
* 1 ISAINT_IDE0 |
129 |
* 2 ISAINT_IDE1 |
130 |
* |
131 |
* NOTE/TODO: Ugly redirection to the ISA controller. |
132 |
*/ |
133 |
n = "P5064_ISAINT"; |
134 |
if (writeflag == MEM_WRITE) { |
135 |
if (idata & ISAINT_IDE0) |
136 |
cpu->machine->isa_pic_data.pic2->ier &= ~0x40; |
137 |
else |
138 |
cpu->machine->isa_pic_data.pic2->ier |= 0x40; |
139 |
if (idata & ISAINT_IDE1) |
140 |
cpu->machine->isa_pic_data.pic2->ier &= ~0x80; |
141 |
else |
142 |
cpu->machine->isa_pic_data.pic2->ier |= 0x80; |
143 |
cpu->machine->isa_pic_data.pic1->ier &= ~0x04; |
144 |
} else { |
145 |
if (cpu->machine->isa_pic_data.pic2->irr & |
146 |
~cpu->machine->isa_pic_data.pic2->ier & 0x40) |
147 |
odata |= ISAINT_IDE0; |
148 |
if (cpu->machine->isa_pic_data.pic2->irr & |
149 |
~cpu->machine->isa_pic_data.pic2->ier & 0x80) |
150 |
odata |= ISAINT_IDE1; |
151 |
|
152 |
/* Read => ack: */ |
153 |
cpu->machine->isa_pic_data.pic2->irr &= ~0xc0; |
154 |
cpu_interrupt_ack(cpu, 2); |
155 |
} |
156 |
break; |
157 |
|
158 |
case P5064_KBDINT: |
159 |
/* |
160 |
* TODO: See how ISAINT is implemented. |
161 |
*/ |
162 |
n = "P5064_KBDINT"; |
163 |
if (writeflag == MEM_READ) |
164 |
odata = 0; |
165 |
break; |
166 |
|
167 |
default:if (writeflag == MEM_READ) { |
168 |
fatal("[ algor: read from 0x%x ]\n", |
169 |
(int)relative_addr); |
170 |
} else { |
171 |
fatal("[ algor: write to 0x%x: 0x%"PRIx64" ]\n", |
172 |
(int) relative_addr, (uint64_t) idata); |
173 |
} |
174 |
} |
175 |
|
176 |
if (n != NULL) { |
177 |
if (writeflag == MEM_READ) { |
178 |
debug("[ algor: read from %s: 0x%"PRIx64" ]\n", |
179 |
n, (uint64_t) odata); |
180 |
} else { |
181 |
debug("[ algor: write to %s: 0x%"PRIx64" ]\n", |
182 |
n, (uint64_t) idata); |
183 |
} |
184 |
} |
185 |
|
186 |
if (writeflag == MEM_READ) |
187 |
memory_writemax64(cpu, data, len, odata); |
188 |
|
189 |
return 1; |
190 |
} |
191 |
|
192 |
|
193 |
DEVINIT(algor) |
194 |
{ |
195 |
struct algor_data *d = malloc(sizeof(struct algor_data)); |
196 |
if (d == NULL) { |
197 |
fprintf(stderr, "out of memory\n"); |
198 |
exit(1); |
199 |
} |
200 |
memset(d, 0, sizeof(struct algor_data)); |
201 |
|
202 |
if (devinit->addr != 0x1ff00000) { |
203 |
fatal("The Algor base address should be 0x1ff00000.\n"); |
204 |
exit(1); |
205 |
} |
206 |
|
207 |
memory_device_register(devinit->machine->memory, devinit->name, |
208 |
devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL); |
209 |
|
210 |
d->base_addr = devinit->addr; |
211 |
|
212 |
devinit->return_ptr = d; |
213 |
|
214 |
return 1; |
215 |
} |
216 |
|