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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_algor.c,v 1.3 2006/08/14 17:45:47 debug Exp $ |
* $Id: dev_algor.c,v 1.6 2007/06/15 18:44:18 debug Exp $ |
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* |
* |
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* Algor misc. stuff. |
* COMMENT: Algor P5064 misc. stuff |
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* |
* |
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* TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc. |
* TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc. |
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* |
* |
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#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
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#include "devices.h" |
#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "algor_p5064reg.h" |
#include "algor_p5064reg.h" |
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struct algor_data { |
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uint64_t base_addr; |
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struct interrupt mips_irq_2; |
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struct interrupt mips_irq_3; |
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struct interrupt mips_irq_4; |
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}; |
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DEVICE_ACCESS(algor) |
DEVICE_ACCESS(algor) |
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{ |
{ |
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struct algor_data *d = extra; |
struct algor_data *d = extra; |
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/* Read => ack: */ |
/* Read => ack: */ |
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cpu->machine->isa_pic_data.pic1->irr &= ~0x18; |
cpu->machine->isa_pic_data.pic1->irr &= ~0x18; |
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cpu_interrupt_ack(cpu, 4); |
INTERRUPT_DEASSERT(d->mips_irq_4); |
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} else { |
} else { |
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if (idata & LOCINT_COM1) |
if (idata & LOCINT_COM1) |
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cpu->machine->isa_pic_data.pic1->ier &= ~0x10; |
cpu->machine->isa_pic_data.pic1->ier &= ~0x10; |
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n = "P5064_PCIINT"; |
n = "P5064_PCIINT"; |
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if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
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odata = 0; |
odata = 0; |
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cpu_interrupt_ack(cpu, 3); |
INTERRUPT_DEASSERT(d->mips_irq_3); |
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} |
} |
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break; |
break; |
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/* Read => ack: */ |
/* Read => ack: */ |
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cpu->machine->isa_pic_data.pic2->irr &= ~0xc0; |
cpu->machine->isa_pic_data.pic2->irr &= ~0xc0; |
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cpu_interrupt_ack(cpu, 2); |
INTERRUPT_DEASSERT(d->mips_irq_2); |
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} |
} |
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break; |
break; |
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DEVINIT(algor) |
DEVINIT(algor) |
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{ |
{ |
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struct algor_data *d = malloc(sizeof(struct algor_data)); |
char tmpstr[200]; |
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if (d == NULL) { |
struct algor_data *d; |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
CHECK_ALLOCATION(d = malloc(sizeof(struct algor_data))); |
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} |
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memset(d, 0, sizeof(struct algor_data)); |
memset(d, 0, sizeof(struct algor_data)); |
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d->base_addr = devinit->addr; |
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if (devinit->addr != 0x1ff00000) { |
if (devinit->addr != 0x1ff00000) { |
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fatal("The Algor base address should be 0x1ff00000.\n"); |
fatal("The Algor base address should be 0x1ff00000.\n"); |
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exit(1); |
exit(1); |
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} |
} |
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/* Connect to MIPS irq 2, 3, and 4: */ |
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snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->mips_irq_2); |
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snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->mips_irq_3); |
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snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path); |
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INTERRUPT_CONNECT(tmpstr, d->mips_irq_4); |
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memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL); |
devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL); |
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d->base_addr = devinit->addr; |
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devinit->return_ptr = d; |
devinit->return_ptr = d; |
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return 1; |
return 1; |