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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_8253.c,v 1.9 2006/02/09 20:02:58 debug Exp $ |
* $Id: dev_8253.c,v 1.14 2006/07/24 19:08:17 debug Exp $ |
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* |
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* 8253/8254 Programmable Interval Timer. |
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* |
* |
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* This is mostly bogus. |
* Intel 8253/8254 Programmable Interval Timer |
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* |
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* TODO: The timers don't really count down. Fix this when there is a generic |
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* clock framework; also split counter[] into reset value and current value. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "i8253reg.h" |
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/* #define debug fatal */ |
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#define DEV_8253_LENGTH 4 |
#define DEV_8253_LENGTH 4 |
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#define TICK_SHIFT 14 |
#define TICK_SHIFT 14 |
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struct pit8253_data { |
struct pit8253_data { |
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int irq_nr; |
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int in_use; |
int in_use; |
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int irq0_nr; |
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int counter_select; |
int counter_select; |
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uint8_t mode_byte; |
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int mode[3]; |
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int counter[3]; |
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}; |
}; |
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/* |
DEVICE_TICK(8253) |
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* dev_8253_tick(): |
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*/ |
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void dev_8253_tick(struct cpu *cpu, void *extra) |
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{ |
{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
struct pit8253_data *d = (struct pit8253_data *) extra; |
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if (!d->in_use) |
if (!d->in_use) |
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return; |
return; |
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cpu_interrupt(cpu, d->irq_nr); |
switch (d->mode[0] & 0x0e) { |
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case I8253_TIMER_INTTC: |
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/* TODO: Correct frequency! */ |
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cpu_interrupt(cpu, d->irq0_nr); |
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break; |
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case I8253_TIMER_RATEGEN: |
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break; |
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default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e); |
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exit(1); |
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} |
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} |
} |
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/* |
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* dev_8253_access(): |
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*/ |
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DEVICE_ACCESS(8253) |
DEVICE_ACCESS(8253) |
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{ |
{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
struct pit8253_data *d = (struct pit8253_data *) extra; |
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d->in_use = 1; |
d->in_use = 1; |
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/* TODO: ack somewhere else */ |
/* TODO: ack somewhere else */ |
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cpu_interrupt_ack(cpu, d->irq_nr); |
cpu_interrupt_ack(cpu, d->irq0_nr); |
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switch (relative_addr) { |
switch (relative_addr) { |
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case 0x00: |
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case I8253_TIMER_CNTR0: |
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case I8253_TIMER_CNTR1: |
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case I8253_TIMER_CNTR2: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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/* TODO */ |
switch (d->mode_byte & 0x30) { |
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case I8253_TIMER_LSB: |
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case I8253_TIMER_16BIT: |
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d->counter[relative_addr] &= 0xff00; |
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d->counter[relative_addr] |= (idata & 0xff); |
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break; |
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case I8253_TIMER_MSB: |
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d->counter[relative_addr] &= 0x00ff; |
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d->counter[relative_addr] |= ((idata&0xff)<<8); |
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debug("[ 8253: counter %i set to %i (%i Hz) " |
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"]\n", relative_addr, d->counter[ |
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relative_addr], (int)(I8253_TIMER_FREQ / |
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(float)d->counter[relative_addr] + 0.5)); |
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break; |
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default:fatal("[ 8253: huh? writing to counter" |
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" %i but neither from msb nor lsb? ]\n", |
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relative_addr); |
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} |
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} else { |
} else { |
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/* TODO */ |
switch (d->mode_byte & 0x30) { |
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/* odata = 1; */ |
case I8253_TIMER_LSB: |
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odata = random(); |
case I8253_TIMER_16BIT: |
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odata = d->counter[relative_addr] & 0xff; |
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break; |
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case I8253_TIMER_MSB: |
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odata = (d->counter[relative_addr] >> 8) & 0xff; |
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break; |
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default:fatal("[ 8253: huh? reading from counter" |
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" %i but neither from msb nor lsb? ]\n", |
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relative_addr); |
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} |
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} |
} |
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/* Switch from LSB to MSB, if accessing as 16-bit word: */ |
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if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT) |
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d->mode_byte &= ~I8253_TIMER_LSB; |
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break; |
break; |
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case 0x03: |
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150 |
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case I8253_TIMER_MODE: |
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if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
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d->mode_byte = idata; |
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d->counter_select = idata >> 6; |
d->counter_select = idata >> 6; |
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/* TODO: other bits */ |
if (d->counter_select > 2) { |
156 |
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debug("[ 8253: attempt to select counter 3," |
157 |
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" which doesn't exist. ]\n"); |
158 |
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d->counter_select = 0; |
159 |
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} |
160 |
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161 |
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d->mode[d->counter_select] = idata & 0x0e; |
162 |
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163 |
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debug("[ 8253: select=%i mode=0x%x ", |
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d->counter_select, d->mode[d->counter_select]); |
165 |
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if (idata & 0x30) { |
166 |
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switch (idata & 0x30) { |
167 |
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case I8253_TIMER_LSB: |
168 |
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debug("LSB "); |
169 |
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break; |
170 |
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case I8253_TIMER_16BIT: |
171 |
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debug("LSB+"); |
172 |
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case I8253_TIMER_MSB: |
173 |
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debug("MSB "); |
174 |
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} |
175 |
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} |
176 |
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debug("]\n"); |
177 |
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178 |
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if (idata & I8253_TIMER_BCD) { |
179 |
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fatal("[ 8253: BCD not yet implemented ]\n"); |
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exit(1); |
181 |
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} |
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} else { |
} else { |
183 |
odata = d->counter_select << 6; |
debug("[ 8253: read; can this actually happen? ]\n"); |
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odata = d->mode_byte; |
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} |
} |
186 |
break; |
break; |
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default: |
|
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if (writeflag == MEM_WRITE) { |
default:if (writeflag == MEM_WRITE) { |
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fatal("[ 8253: unimplemented write to address 0x%x" |
fatal("[ 8253: unimplemented write to address 0x%x" |
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" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
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} else { |
} else { |
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fatal("[ 8253: unimplemented read from address 0x%x " |
fatal("[ 8253: unimplemented read from address 0x%x " |
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"]\n", (int)relative_addr); |
"]\n", (int)relative_addr); |
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} |
} |
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exit(1); |
196 |
} |
} |
197 |
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if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
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exit(1); |
exit(1); |
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} |
} |
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memset(d, 0, sizeof(struct pit8253_data)); |
memset(d, 0, sizeof(struct pit8253_data)); |
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d->irq_nr = devinit->irq_nr; |
d->irq0_nr = devinit->irq_nr; |
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d->in_use = devinit->in_use; |
d->in_use = devinit->in_use; |
216 |
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217 |
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/* Don't cause interrupt, by default. */ |
218 |
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d->mode[0] = I8253_TIMER_RATEGEN; |
219 |
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d->mode[1] = I8253_TIMER_RATEGEN; |
220 |
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d->mode[2] = I8253_TIMER_RATEGEN; |
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memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d, |
devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d, |
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DM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
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machine_add_tickfunction(devinit->machine, dev_8253_tick, |
machine_add_tickfunction(devinit->machine, dev_8253_tick, |
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d, TICK_SHIFT); |
d, TICK_SHIFT, 0.0); |
228 |
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229 |
return 1; |
return 1; |
230 |
} |
} |