1 |
/* |
/* |
2 |
* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: bus_pci.c,v 1.65 2006/05/10 03:32:32 debug Exp $ |
* $Id: bus_pci.c,v 1.85 2007/06/16 14:39:18 debug Exp $ |
29 |
* |
* |
30 |
* Generic PCI bus framework. This is not a normal "device", but is used by |
* COMMENT: Generic PCI bus framework |
31 |
* individual PCI controllers and devices. |
* |
32 |
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* This is not a normal "device", but is used by individual PCI controllers |
33 |
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* and devices. |
34 |
* |
* |
35 |
* See NetBSD's pcidevs.h for more PCI vendor and device identifiers. |
* See NetBSD's pcidevs.h for more PCI vendor and device identifiers. |
36 |
* |
* |
50 |
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51 |
#define BUS_PCI_C |
#define BUS_PCI_C |
52 |
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53 |
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#include "bus_isa.h" |
54 |
#include "bus_pci.h" |
#include "bus_pci.h" |
55 |
#include "cpu.h" |
#include "cpu.h" |
56 |
#include "device.h" |
#include "device.h" |
60 |
#include "memory.h" |
#include "memory.h" |
61 |
#include "misc.h" |
#include "misc.h" |
62 |
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63 |
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#include "cpc700reg.h" |
64 |
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#include "wdc.h" |
65 |
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66 |
extern int verbose; |
extern int verbose; |
67 |
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68 |
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153 |
pci_data->last_was_write_ffffffff = 1; |
pci_data->last_was_write_ffffffff = 1; |
154 |
return; |
return; |
155 |
} |
} |
156 |
/* Writes are not really supported yet: */ |
|
157 |
if (idata != x) { |
if (dev->cfg_reg_write != NULL) { |
158 |
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dev->cfg_reg_write(dev, pci_data->cur_reg, *data); |
159 |
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} else { |
160 |
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/* Print a warning for unhandled writes: */ |
161 |
debug("[ bus_pci: write to PCI DATA: data = 0x%08llx" |
debug("[ bus_pci: write to PCI DATA: data = 0x%08llx" |
162 |
" differs from current value 0x%08llx; NOT YET" |
" (current value = 0x%08llx); NOT YET" |
163 |
" SUPPORTED. bus %i, device %i, function %i (%s)" |
" SUPPORTED. bus %i, device %i, function %i (%s)" |
164 |
" register 0x%02x ]\n", (long long)idata, |
" register 0x%02x ]\n", (long long)idata, |
165 |
(long long)x, pci_data->cur_bus, |
(long long)x, pci_data->cur_bus, |
166 |
pci_data->cur_device, pci_data->cur_func, |
pci_data->cur_device, pci_data->cur_func, |
167 |
dev->name, pci_data->cur_reg); |
dev->name, pci_data->cur_reg); |
168 |
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169 |
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/* Special warning, to detect if NetBSD's special |
170 |
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detection of PCI devices fails: */ |
171 |
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if (pci_data->cur_reg == PCI_COMMAND_STATUS_REG |
172 |
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&& !((*data) & PCI_COMMAND_IO_ENABLE)) { |
173 |
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fatal("\n[ NetBSD PCI detection stuff not" |
174 |
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" yet implemented for device '%s' ]\n", |
175 |
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dev->name); |
176 |
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} |
177 |
} |
} |
178 |
return; |
return; |
179 |
} |
} |
207 |
pci_data->cur_device = device; |
pci_data->cur_device = device; |
208 |
pci_data->cur_func = function; |
pci_data->cur_func = function; |
209 |
pci_data->cur_reg = reg; |
pci_data->cur_reg = reg; |
210 |
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debug("bus_pci_setaddr( bus %d device 0x%x func 0x%x reg 0x%x )\n", bus, device, function, reg ); |
211 |
} |
} |
212 |
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213 |
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226 |
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227 |
if (pci_data == NULL) { |
if (pci_data == NULL) { |
228 |
fatal("bus_pci_add(): pci_data == NULL!\n"); |
fatal("bus_pci_add(): pci_data == NULL!\n"); |
229 |
exit(1); |
abort(); |
230 |
} |
} |
231 |
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|
232 |
/* Find the PCI device: */ |
/* Find the PCI device: */ |
244 |
pd = pd->next; |
pd = pd->next; |
245 |
} |
} |
246 |
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|
247 |
pd = malloc(sizeof(struct pci_device)); |
CHECK_ALLOCATION(pd = malloc(sizeof(struct pci_device))); |
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if (pd == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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248 |
memset(pd, 0, sizeof(struct pci_device)); |
memset(pd, 0, sizeof(struct pci_device)); |
249 |
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250 |
/* Add the new device first in the PCI bus' chain: */ |
/* Add the new device first in the PCI bus' chain: */ |
251 |
pd->next = pci_data->first_device; |
pd->next = pci_data->first_device; |
252 |
pci_data->first_device = pd; |
pci_data->first_device = pd; |
253 |
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254 |
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CHECK_ALLOCATION(pd->name = strdup(name)); |
255 |
pd->pcibus = pci_data; |
pd->pcibus = pci_data; |
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pd->name = strdup(name); |
|
256 |
pd->bus = bus; |
pd->bus = bus; |
257 |
pd->device = device; |
pd->device = device; |
258 |
pd->function = function; |
pd->function = function; |
338 |
} |
} |
339 |
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340 |
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static void bus_pci_debug_dump__2(struct pci_device *pd) |
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{ |
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if (pd == NULL) |
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return; |
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bus_pci_debug_dump__2(pd->next); |
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debug("bus %3i, dev %2i, func %i: %s\n", |
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pd->bus, pd->device, pd->function, pd->name); |
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} |
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/* |
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* bus_pci_debug_dump(): |
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* |
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* Lists the attached PCI devices (in reverse). |
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*/ |
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void bus_pci_debug_dump(void *extra) |
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{ |
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struct pci_data *d = (struct pci_data *) extra; |
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int iadd = DEBUG_INDENTATION; |
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debug("pci:\n"); |
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debug_indentation(iadd); |
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if (d->first_device == NULL) |
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debug("no devices!\n"); |
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else |
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bus_pci_debug_dump__2(d->first_device); |
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debug_indentation(-iadd); |
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} |
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341 |
/* |
/* |
342 |
* bus_pci_init(): |
* bus_pci_init(): |
343 |
* |
* |
344 |
* This doesn't register a device, but instead returns a pointer to a struct |
* This doesn't register a device, but instead returns a pointer to a struct |
345 |
* which should be passed to other bus_pci functions when accessing the bus. |
* which should be passed to other bus_pci functions when accessing the bus. |
346 |
* |
* |
347 |
* irq_nr is the (optional) IRQ nr that this PCI bus interrupts at. |
* irq_path is the interrupt path to the PCI controller. |
348 |
* |
* |
349 |
* pci_portbase, pci_membase, and pci_irqbase are the port, memory, and |
* pci_portbase, pci_membase, and pci_irqbase are the port, memory, and |
350 |
* interrupt bases for PCI devices (as found in the configuration registers). |
* interrupt bases for PCI devices (as found in the configuration registers). |
355 |
* isa_portbase, isa_membase, and isa_irqbase are the port, memory, and |
* isa_portbase, isa_membase, and isa_irqbase are the port, memory, and |
356 |
* interrupt bases for legacy ISA devices. |
* interrupt bases for legacy ISA devices. |
357 |
*/ |
*/ |
358 |
struct pci_data *bus_pci_init(struct machine *machine, int irq_nr, |
struct pci_data *bus_pci_init(struct machine *machine, char *irq_path, |
359 |
uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, |
uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, |
360 |
uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase, |
uint64_t pci_portbase, uint64_t pci_membase, char *pci_irqbase, |
361 |
uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase) |
uint64_t isa_portbase, uint64_t isa_membase, char *isa_irqbase) |
362 |
{ |
{ |
363 |
struct pci_data *d; |
struct pci_data *d; |
364 |
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|
365 |
d = malloc(sizeof(struct pci_data)); |
CHECK_ALLOCATION(d = malloc(sizeof(struct pci_data))); |
|
if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
|
366 |
memset(d, 0, sizeof(struct pci_data)); |
memset(d, 0, sizeof(struct pci_data)); |
367 |
d->irq_nr = irq_nr; |
|
368 |
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CHECK_ALLOCATION(d->irq_path = strdup(irq_path)); |
369 |
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CHECK_ALLOCATION(d->irq_path_isa = strdup(isa_irqbase)); |
370 |
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CHECK_ALLOCATION(d->irq_path_pci = strdup(pci_irqbase)); |
371 |
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372 |
d->pci_actual_io_offset = pci_actual_io_offset; |
d->pci_actual_io_offset = pci_actual_io_offset; |
373 |
d->pci_actual_mem_offset = pci_actual_mem_offset; |
d->pci_actual_mem_offset = pci_actual_mem_offset; |
374 |
d->pci_portbase = pci_portbase; |
d->pci_portbase = pci_portbase; |
375 |
d->pci_membase = pci_membase; |
d->pci_membase = pci_membase; |
|
d->pci_irqbase = pci_irqbase; |
|
376 |
d->isa_portbase = isa_portbase; |
d->isa_portbase = isa_portbase; |
377 |
d->isa_membase = isa_membase; |
d->isa_membase = isa_membase; |
|
d->isa_irqbase = isa_irqbase; |
|
378 |
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|
379 |
/* Register the bus: */ |
d->cur_pci_portbase = d->pci_portbase; |
380 |
machine_bus_register(machine, "pci", bus_pci_debug_dump, d); |
d->cur_pci_membase = d->pci_membase; |
381 |
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|
382 |
/* Assume that the first 64KB could be used by legacy ISA devices: */ |
/* Assume that the first 64KB could be used by legacy ISA devices: */ |
383 |
d->cur_pci_portbase = d->pci_portbase + 0x10000; |
if (d->isa_portbase != 0 || d->isa_membase != 0) { |
384 |
d->cur_pci_membase = d->pci_membase + 0x10000; |
d->cur_pci_portbase += 0x10000; |
385 |
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d->cur_pci_membase += 0x10000; |
386 |
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} |
387 |
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388 |
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debug("bus_pci_init( pci_actual_io_offset %x pci_actual_mem_offset 0x%x pci_portbase 0x%x pci_membase 0x%x isa_portbase %x isa_membase %x )\n", pci_actual_io_offset, pci_actual_mem_offset, pci_portbase, pci_membase, isa_portbase, isa_membase ); |
389 |
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390 |
return d; |
return d; |
391 |
} |
} |
404 |
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405 |
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406 |
/* |
/* |
407 |
* Integraphics Systems "igsfb" Framebuffer (graphics) card. |
* Integraphics Systems "igsfb" Framebuffer (graphics) card, used in at |
408 |
* |
* least the NetWinder. |
|
* TODO |
|
409 |
*/ |
*/ |
410 |
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411 |
#define PCI_VENDOR_INTEGRAPHICS 0x10ea |
#define PCI_VENDOR_INTEGRAPHICS 0x10ea |
412 |
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413 |
PCIINIT(igsfb) |
PCIINIT(igsfb) |
414 |
{ |
{ |
415 |
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char tmpstr[200]; |
416 |
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|
417 |
PCI_SET_DATA(PCI_ID_REG, |
PCI_SET_DATA(PCI_ID_REG, |
418 |
PCI_ID_CODE(PCI_VENDOR_INTEGRAPHICS, 0x2010)); |
PCI_ID_CODE(PCI_VENDOR_INTEGRAPHICS, 0x2010)); |
419 |
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|
424 |
/* TODO */ |
/* TODO */ |
425 |
PCI_SET_DATA(0x10, 0x08000000); |
PCI_SET_DATA(0x10, 0x08000000); |
426 |
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|
427 |
dev_vga_init(machine, mem, pd->pcibus->isa_membase + 0xa0000, |
snprintf(tmpstr, sizeof(tmpstr), "igsfb addr=0x%llx", |
428 |
0x88800000 + 0x3c0, machine->machine_name); |
(long long)(pd->pcibus->isa_membase + 0x08000000)); |
429 |
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device_add(machine, tmpstr); |
430 |
} |
} |
431 |
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432 |
|
|
479 |
/* Linux uses these to detect which IRQ the IDE controller uses: */ |
/* Linux uses these to detect which IRQ the IDE controller uses: */ |
480 |
PCI_SET_DATA(0x44, 0x0000000e); |
PCI_SET_DATA(0x44, 0x0000000e); |
481 |
PCI_SET_DATA(0x58, 0x00000003); |
PCI_SET_DATA(0x58, 0x00000003); |
482 |
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|
483 |
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switch (machine->machine_type) { |
484 |
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case MACHINE_CATS: |
485 |
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bus_isa_init(machine, pd->pcibus->irq_path_isa, |
486 |
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BUS_ISA_PCKBC_FORCE_USE | BUS_ISA_PCKBC_NONPCSTYLE, |
487 |
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0x7c000000, 0x80000000); |
488 |
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break; |
489 |
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default:fatal("ali_m1543 init: unimplemented machine type\n"); |
490 |
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exit(1); |
491 |
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} |
492 |
} |
} |
493 |
|
|
494 |
PCIINIT(ali_m5229) |
PCIINIT(ali_m5229) |
495 |
{ |
{ |
496 |
char tmpstr[300]; |
char tmpstr[300], irqstr[300]; |
497 |
|
|
498 |
PCI_SET_DATA(PCI_ID_REG, |
PCI_SET_DATA(PCI_ID_REG, |
499 |
PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5229)); |
PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5229)); |
501 |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
502 |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1); |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1); |
503 |
|
|
504 |
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switch (machine->machine_type) { |
505 |
|
case MACHINE_CATS: |
506 |
|
/* CATS ISA interrupts are at footbridge irq 10: */ |
507 |
|
snprintf(irqstr, sizeof(irqstr), "%s.10.isa", |
508 |
|
pd->pcibus->irq_path); |
509 |
|
break; |
510 |
|
default:fatal("ali_m5229 init: unimplemented machine type\n"); |
511 |
|
exit(1); |
512 |
|
} |
513 |
|
|
514 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
515 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
516 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i", |
517 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
518 |
pd->pcibus->isa_irqbase + 14); |
irqstr, 14); |
519 |
device_add(machine, tmpstr); |
device_add(machine, tmpstr); |
520 |
} |
} |
521 |
|
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633 |
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|
634 |
|
|
635 |
/* |
/* |
636 |
|
* AMD PCnet Ethernet card. |
637 |
|
* |
638 |
|
* "Am79c970A PCnet-PCI II rev 0" or similar. |
639 |
|
*/ |
640 |
|
|
641 |
|
#define PCI_VENDOR_AMD 0x1022 /* Advanced Micro Devices */ |
642 |
|
#define PCI_PRODUCT_AMD_PCNET_PCI 0x2000 /* PCnet-PCI Ethernet */ |
643 |
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|
644 |
|
PCIINIT(pcn) |
645 |
|
{ |
646 |
|
int irq; |
647 |
|
|
648 |
|
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_AMD, |
649 |
|
PCI_PRODUCT_AMD_PCNET_PCI)); |
650 |
|
|
651 |
|
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK, |
652 |
|
PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x00); /* Revision 0 */ |
653 |
|
|
654 |
|
switch (machine->machine_type) { |
655 |
|
|
656 |
|
case MACHINE_EVBMIPS: |
657 |
|
irq = (1 << 8) + 10; /* TODO */ |
658 |
|
break; |
659 |
|
|
660 |
|
default:fatal("pcn in non-implemented machine type %i\n", |
661 |
|
machine->machine_type); |
662 |
|
exit(1); |
663 |
|
} |
664 |
|
|
665 |
|
PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq); |
666 |
|
|
667 |
|
/* |
668 |
|
* TODO: Add the pcn device here. The pcn device will need to work as |
669 |
|
* a wrapper for dev_le + all the DMA magic and whatever is required. |
670 |
|
* It's too much to implement right now. |
671 |
|
*/ |
672 |
|
} |
673 |
|
|
674 |
|
|
675 |
|
|
676 |
|
/* |
677 |
* Intel 31244 Serial ATA Controller |
* Intel 31244 Serial ATA Controller |
678 |
* Intel 82371SB PIIX3 PCI-ISA bridge |
* Intel 82371SB PIIX3 PCI-ISA bridge |
679 |
* Intel 82371AB PIIX4 PCI-ISA bridge |
* Intel 82371AB PIIX4 PCI-ISA bridge |
720 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
721 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
722 |
char tmpstr[150]; |
char tmpstr[150]; |
723 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i", |
724 |
(long long)(pd->pcibus->pci_actual_io_offset + 0), |
(long long)(pd->pcibus->pci_actual_io_offset + 0), |
725 |
pd->pcibus->pci_irqbase + 0); |
pd->pcibus->irq_path_pci, irq & 255); |
726 |
device_add(machine, tmpstr); |
device_add(machine, tmpstr); |
727 |
} |
} |
728 |
} |
} |
768 |
PCI_SET_DATA(0x60, 0x0f0e0b0a); |
PCI_SET_DATA(0x60, 0x0f0e0b0a); |
769 |
} |
} |
770 |
|
|
771 |
|
struct piix_ide_extra { |
772 |
|
void *wdc0; |
773 |
|
void *wdc1; |
774 |
|
}; |
775 |
|
|
776 |
|
int piix_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value) |
777 |
|
{ |
778 |
|
void *wdc0 = ((struct piix_ide_extra *)pd->extra)->wdc0; |
779 |
|
void *wdc1 = ((struct piix_ide_extra *)pd->extra)->wdc1; |
780 |
|
int enabled = 0; |
781 |
|
|
782 |
|
switch (reg) { |
783 |
|
case PCI_COMMAND_STATUS_REG: |
784 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
785 |
|
enabled = 1; |
786 |
|
if (wdc0 != NULL) |
787 |
|
wdc_set_io_enabled(wdc0, enabled); |
788 |
|
if (wdc1 != NULL) |
789 |
|
wdc_set_io_enabled(wdc1, enabled); |
790 |
|
return 1; |
791 |
|
} |
792 |
|
|
793 |
|
return 0; |
794 |
|
} |
795 |
|
|
796 |
PCIINIT(piix3_ide) |
PCIINIT(piix3_ide) |
797 |
{ |
{ |
798 |
char tmpstr[100]; |
char tmpstr[100]; |
808 |
/* channel 0 and 1 enabled as IDE */ |
/* channel 0 and 1 enabled as IDE */ |
809 |
PCI_SET_DATA(0x40, 0x80008000); |
PCI_SET_DATA(0x40, 0x80008000); |
810 |
|
|
811 |
|
CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra))); |
812 |
|
((struct piix_ide_extra *)pd->extra)->wdc0 = NULL; |
813 |
|
((struct piix_ide_extra *)pd->extra)->wdc1 = NULL; |
814 |
|
|
815 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
816 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
817 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx " |
818 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase + |
819 |
pd->pcibus->isa_irqbase + 14); |
0x1f0), pd->pcibus->irq_path_isa, 14); |
820 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc0 = |
821 |
|
device_add(machine, tmpstr); |
822 |
} |
} |
823 |
|
|
824 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
825 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
826 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx " |
827 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase + |
828 |
pd->pcibus->isa_irqbase + 15); |
0x170), pd->pcibus->irq_path_isa, 15); |
829 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc1 = |
830 |
|
device_add(machine, tmpstr); |
831 |
} |
} |
832 |
|
|
833 |
|
pd->cfg_reg_write = piix_ide_cfg_reg_write; |
834 |
} |
} |
835 |
|
|
836 |
PCIINIT(piix4_ide) |
PCIINIT(piix4_ide) |
848 |
/* channel 0 and 1 enabled as IDE */ |
/* channel 0 and 1 enabled as IDE */ |
849 |
PCI_SET_DATA(0x40, 0x80008000); |
PCI_SET_DATA(0x40, 0x80008000); |
850 |
|
|
851 |
|
CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra))); |
852 |
|
((struct piix_ide_extra *)pd->extra)->wdc0 = NULL; |
853 |
|
((struct piix_ide_extra *)pd->extra)->wdc1 = NULL; |
854 |
|
|
855 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
856 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
857 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
858 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0), |
859 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->irq_path_isa, 14); |
860 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc0 = |
861 |
|
device_add(machine, tmpstr); |
862 |
} |
} |
863 |
|
|
864 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
865 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
866 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
867 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170), |
868 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->irq_path_isa, 15); |
869 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc1 = |
870 |
|
device_add(machine, tmpstr); |
871 |
} |
} |
872 |
|
|
873 |
|
pd->cfg_reg_write = piix_ide_cfg_reg_write; |
874 |
} |
} |
875 |
|
|
876 |
|
|
915 |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
916 |
} |
} |
917 |
|
|
918 |
|
/* |
919 |
|
* Sandpoint host bridge based on uninorth |
920 |
|
*/ |
921 |
|
|
922 |
|
#define PCI_VENDOR_MOT 0x1057 |
923 |
|
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 |
924 |
|
#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 |
925 |
|
|
926 |
|
PCIINIT(mpc10x) |
927 |
|
{ |
928 |
|
uint64_t port, memaddr; |
929 |
|
|
930 |
|
debug("sandpoint mpx10x host bridge\n"); |
931 |
|
|
932 |
|
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_MOT, |
933 |
|
PCI_DEVICE_ID_MOTOROLA_MPC107)); /* FIXME MPC106 ?? */ |
934 |
|
|
935 |
|
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_BRIDGE, |
936 |
|
PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x00); /* Revision? */ |
937 |
|
|
938 |
|
PCI_SET_DATA(PCI_BHLC_REG, |
939 |
|
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
940 |
|
|
941 |
|
allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr); |
942 |
|
|
943 |
|
} |
944 |
|
|
945 |
|
|
946 |
|
|
947 |
/* |
/* |
971 |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
972 |
} |
} |
973 |
|
|
974 |
|
struct vt82c586_ide_extra { |
975 |
|
void *wdc0; |
976 |
|
void *wdc1; |
977 |
|
}; |
978 |
|
|
979 |
|
int vt82c586_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value) |
980 |
|
{ |
981 |
|
void *wdc0 = ((struct vt82c586_ide_extra *)pd->extra)->wdc0; |
982 |
|
void *wdc1 = ((struct vt82c586_ide_extra *)pd->extra)->wdc1; |
983 |
|
int enabled = 0; |
984 |
|
|
985 |
|
switch (reg) { |
986 |
|
case PCI_COMMAND_STATUS_REG: |
987 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
988 |
|
enabled = 1; |
989 |
|
if (wdc0 != NULL) |
990 |
|
wdc_set_io_enabled(wdc0, enabled); |
991 |
|
if (wdc1 != NULL) |
992 |
|
wdc_set_io_enabled(wdc1, enabled); |
993 |
|
return 1; |
994 |
|
} |
995 |
|
|
996 |
|
return 0; |
997 |
|
} |
998 |
|
|
999 |
PCIINIT(vt82c586_ide) |
PCIINIT(vt82c586_ide) |
1000 |
{ |
{ |
1001 |
char tmpstr[100]; |
char tmpstr[100]; |
1011 |
/* channel 0 and 1 enabled */ |
/* channel 0 and 1 enabled */ |
1012 |
PCI_SET_DATA(0x40, 0x00000003); |
PCI_SET_DATA(0x40, 0x00000003); |
1013 |
|
|
1014 |
|
CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct vt82c586_ide_extra))); |
1015 |
|
((struct vt82c586_ide_extra *)pd->extra)->wdc0 = NULL; |
1016 |
|
((struct vt82c586_ide_extra *)pd->extra)->wdc1 = NULL; |
1017 |
|
|
1018 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
1019 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
1020 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1021 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0), |
1022 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->irq_path_isa, 14); |
1023 |
device_add(machine, tmpstr); |
((struct vt82c586_ide_extra *)pd->extra)->wdc0 = |
1024 |
|
device_add(machine, tmpstr); |
1025 |
} |
} |
1026 |
|
|
1027 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
1028 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
1029 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1030 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170), |
1031 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->irq_path_isa, 15); |
1032 |
device_add(machine, tmpstr); |
((struct vt82c586_ide_extra *)pd->extra)->wdc1 = |
1033 |
|
device_add(machine, tmpstr); |
1034 |
} |
} |
1035 |
|
|
1036 |
|
pd->cfg_reg_write = vt82c586_ide_cfg_reg_write; |
1037 |
} |
} |
1038 |
|
|
1039 |
|
|
1057 |
|
|
1058 |
PCI_SET_DATA(PCI_BHLC_REG, |
PCI_SET_DATA(PCI_BHLC_REG, |
1059 |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
1060 |
|
|
1061 |
|
switch (machine->machine_type) { |
1062 |
|
case MACHINE_NETWINDER: |
1063 |
|
bus_isa_init(machine, pd->pcibus->irq_path_isa, |
1064 |
|
0, 0x7c000000, 0x80000000); |
1065 |
|
break; |
1066 |
|
default:fatal("symphony_83c553 init: unimplemented machine type\n"); |
1067 |
|
exit(1); |
1068 |
|
} |
1069 |
|
} |
1070 |
|
|
1071 |
|
struct symphony_82c105_extra { |
1072 |
|
void *wdc0; |
1073 |
|
void *wdc1; |
1074 |
|
}; |
1075 |
|
|
1076 |
|
int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg, |
1077 |
|
uint32_t value) |
1078 |
|
{ |
1079 |
|
void *wdc0 = ((struct symphony_82c105_extra *)pd->extra)->wdc0; |
1080 |
|
void *wdc1 = ((struct symphony_82c105_extra *)pd->extra)->wdc1; |
1081 |
|
int enabled = 0; |
1082 |
|
|
1083 |
|
printf("reg = 0x%x\n", reg); |
1084 |
|
switch (reg) { |
1085 |
|
case PCI_COMMAND_STATUS_REG: |
1086 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
1087 |
|
enabled = 1; |
1088 |
|
printf(" value = 0x%"PRIx32"\n", value); |
1089 |
|
if (wdc0 != NULL) |
1090 |
|
wdc_set_io_enabled(wdc0, enabled); |
1091 |
|
if (wdc1 != NULL) |
1092 |
|
wdc_set_io_enabled(wdc1, enabled); |
1093 |
|
/* Set all bits: */ |
1094 |
|
PCI_SET_DATA(reg, value); |
1095 |
|
return 1; |
1096 |
|
case PCI_MAPREG_START: |
1097 |
|
case PCI_MAPREG_START + 4: |
1098 |
|
case PCI_MAPREG_START + 8: |
1099 |
|
case PCI_MAPREG_START + 12: |
1100 |
|
case PCI_MAPREG_START + 16: |
1101 |
|
case PCI_MAPREG_START + 20: |
1102 |
|
PCI_SET_DATA(reg, value); |
1103 |
|
return 1; |
1104 |
|
} |
1105 |
|
|
1106 |
|
return 0; |
1107 |
} |
} |
1108 |
|
|
1109 |
PCIINIT(symphony_82c105) |
PCIINIT(symphony_82c105) |
1117 |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
1118 |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05); |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05); |
1119 |
|
|
1120 |
|
/* TODO: Interrupt line: */ |
1121 |
|
/* PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000); */ |
1122 |
|
|
1123 |
/* APO_IDECONF */ |
/* APO_IDECONF */ |
1124 |
/* channel 0 and 1 enabled */ |
/* channel 0 and 1 enabled */ |
1125 |
PCI_SET_DATA(0x40, 0x00000003); |
PCI_SET_DATA(0x40, 0x00000003); |
1126 |
|
|
1127 |
|
CHECK_ALLOCATION(pd->extra = |
1128 |
|
malloc(sizeof(struct symphony_82c105_extra))); |
1129 |
|
((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL; |
1130 |
|
((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL; |
1131 |
|
|
1132 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
1133 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
1134 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1135 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0), |
1136 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->irq_path_isa, 14); |
1137 |
device_add(machine, tmpstr); |
((struct symphony_82c105_extra *)pd->extra)->wdc0 = |
1138 |
|
device_add(machine, tmpstr); |
1139 |
} |
} |
1140 |
|
|
1141 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
1142 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
1143 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1144 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170), |
1145 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->irq_path_isa, 15); |
1146 |
device_add(machine, tmpstr); |
((struct symphony_82c105_extra *)pd->extra)->wdc1 = |
1147 |
|
device_add(machine, tmpstr); |
1148 |
} |
} |
1149 |
|
|
1150 |
|
pd->cfg_reg_write = symphony_82c105_cfg_reg_write; |
1151 |
|
} |
1152 |
|
|
1153 |
|
|
1154 |
|
|
1155 |
|
/* |
1156 |
|
* Realtek 8139C+ PCI ethernet. |
1157 |
|
*/ |
1158 |
|
|
1159 |
|
#define PCI_VENDOR_REALTEK 0x10ec |
1160 |
|
#define PCI_PRODUCT_REALTEK_RT8139 0x8139 |
1161 |
|
|
1162 |
|
PCIINIT(rtl8139c) |
1163 |
|
{ |
1164 |
|
uint64_t port, memaddr; |
1165 |
|
int pci_int_line = 0x101, irq = 0; |
1166 |
|
char irqstr[200]; |
1167 |
|
char tmpstr[200]; |
1168 |
|
|
1169 |
|
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_REALTEK, |
1170 |
|
PCI_PRODUCT_REALTEK_RT8139)); |
1171 |
|
|
1172 |
|
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK, |
1173 |
|
PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x20); |
1174 |
|
|
1175 |
|
switch (machine->machine_type) { |
1176 |
|
case MACHINE_LANDISK: |
1177 |
|
irq = 5; |
1178 |
|
pci_int_line = 0x105; |
1179 |
|
break; |
1180 |
|
default:fatal("rtl8139c for this machine has not been " |
1181 |
|
"implemented yet\n"); |
1182 |
|
exit(1); |
1183 |
|
} |
1184 |
|
|
1185 |
|
PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line); |
1186 |
|
|
1187 |
|
allocate_device_space(pd, 0x100, 0, &port, &memaddr); |
1188 |
|
|
1189 |
|
snprintf(irqstr, sizeof(irqstr), "%s.%i", |
1190 |
|
pd->pcibus->irq_path_pci, irq); |
1191 |
|
|
1192 |
|
snprintf(tmpstr, sizeof(tmpstr), "rtl8139c addr=0x%llx " |
1193 |
|
"irq=%s pci_little_endian=1", (long long)port, irqstr); |
1194 |
|
|
1195 |
|
device_add(machine, tmpstr); |
1196 |
} |
} |
1197 |
|
|
1198 |
|
|
1207 |
PCIINIT(dec21143) |
PCIINIT(dec21143) |
1208 |
{ |
{ |
1209 |
uint64_t port, memaddr; |
uint64_t port, memaddr; |
1210 |
int irq = 0; /* TODO */ |
int pci_int_line = 0x101, irq = 0, isa = 0; |
1211 |
int pci_int_line = 0x101; |
char irqstr[200]; |
1212 |
char tmpstr[200]; |
char tmpstr[200]; |
1213 |
|
|
1214 |
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC, |
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC, |
1232 |
irq = 8 + 7; |
irq = 8 + 7; |
1233 |
pci_int_line = 0x407; |
pci_int_line = 0x407; |
1234 |
break; |
break; |
|
case MACHINE_ALGOR: |
|
|
/* TODO */ |
|
|
irq = 8 + 7; |
|
|
pci_int_line = 0x407; |
|
|
break; |
|
1235 |
case MACHINE_PREP: |
case MACHINE_PREP: |
1236 |
irq = 32 + 10; |
irq = 10; |
1237 |
|
isa = 1; |
1238 |
pci_int_line = 0x20a; |
pci_int_line = 0x20a; |
1239 |
break; |
break; |
1240 |
case MACHINE_MVMEPPC: |
case MACHINE_MVMEPPC: |
1241 |
/* TODO */ |
/* TODO */ |
1242 |
irq = 32 + 10; |
irq = 10; |
1243 |
pci_int_line = 0x40a; |
pci_int_line = 0x40a; |
1244 |
break; |
break; |
1245 |
case MACHINE_PMPPC: |
case MACHINE_PMPPC: |
1246 |
/* TODO, not working yet */ |
/* TODO, not working yet */ |
1247 |
irq = 31 - 21; |
irq = 31 - CPC_IB_EXT1; |
1248 |
pci_int_line = 0x201; |
pci_int_line = 0x101; |
1249 |
break; |
break; |
1250 |
case MACHINE_MACPPC: |
case MACHINE_MACPPC: |
1251 |
/* TODO, not working yet */ |
/* TODO, not working yet */ |
1258 |
|
|
1259 |
allocate_device_space(pd, 0x100, 0x100, &port, &memaddr); |
allocate_device_space(pd, 0x100, 0x100, &port, &memaddr); |
1260 |
|
|
1261 |
|
if (isa) |
1262 |
|
snprintf(irqstr, sizeof(irqstr), "%s.isa.%i", |
1263 |
|
pd->pcibus->irq_path_isa, irq); |
1264 |
|
else |
1265 |
|
snprintf(irqstr, sizeof(irqstr), "%s.%i", |
1266 |
|
pd->pcibus->irq_path_pci, irq); |
1267 |
|
|
1268 |
snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx " |
snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx " |
1269 |
"irq=%i pci_little_endian=1", (long long)port, (long long)memaddr, |
"irq=%s pci_little_endian=1", (long long)port, |
1270 |
irq); |
(long long)memaddr, irqstr); |
1271 |
|
|
1272 |
device_add(machine, tmpstr); |
device_add(machine, tmpstr); |
1273 |
} |
} |
1274 |
|
|