1 |
/* |
/* |
2 |
* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: bus_pci.c,v 1.65 2006/05/10 03:32:32 debug Exp $ |
* $Id: bus_pci.c,v 1.80 2007/02/11 10:03:55 debug Exp $ |
29 |
* |
* |
30 |
* Generic PCI bus framework. This is not a normal "device", but is used by |
* Generic PCI bus framework. This is not a normal "device", but is used by |
31 |
* individual PCI controllers and devices. |
* individual PCI controllers and devices. |
48 |
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49 |
#define BUS_PCI_C |
#define BUS_PCI_C |
50 |
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51 |
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#include "bus_isa.h" |
52 |
#include "bus_pci.h" |
#include "bus_pci.h" |
53 |
#include "cpu.h" |
#include "cpu.h" |
54 |
#include "device.h" |
#include "device.h" |
58 |
#include "memory.h" |
#include "memory.h" |
59 |
#include "misc.h" |
#include "misc.h" |
60 |
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61 |
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#include "wdc.h" |
62 |
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63 |
extern int verbose; |
extern int verbose; |
64 |
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65 |
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150 |
pci_data->last_was_write_ffffffff = 1; |
pci_data->last_was_write_ffffffff = 1; |
151 |
return; |
return; |
152 |
} |
} |
153 |
/* Writes are not really supported yet: */ |
|
154 |
if (idata != x) { |
if (dev->cfg_reg_write != NULL) { |
155 |
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dev->cfg_reg_write(dev, pci_data->cur_reg, *data); |
156 |
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} else { |
157 |
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/* Print a warning for unhandled writes: */ |
158 |
debug("[ bus_pci: write to PCI DATA: data = 0x%08llx" |
debug("[ bus_pci: write to PCI DATA: data = 0x%08llx" |
159 |
" differs from current value 0x%08llx; NOT YET" |
" (current value = 0x%08llx); NOT YET" |
160 |
" SUPPORTED. bus %i, device %i, function %i (%s)" |
" SUPPORTED. bus %i, device %i, function %i (%s)" |
161 |
" register 0x%02x ]\n", (long long)idata, |
" register 0x%02x ]\n", (long long)idata, |
162 |
(long long)x, pci_data->cur_bus, |
(long long)x, pci_data->cur_bus, |
163 |
pci_data->cur_device, pci_data->cur_func, |
pci_data->cur_device, pci_data->cur_func, |
164 |
dev->name, pci_data->cur_reg); |
dev->name, pci_data->cur_reg); |
165 |
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|
166 |
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/* Special warning, to detect if NetBSD's special |
167 |
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detection of PCI devices fails: */ |
168 |
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if (pci_data->cur_reg == PCI_COMMAND_STATUS_REG |
169 |
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&& !((*data) & PCI_COMMAND_IO_ENABLE)) { |
170 |
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fatal("\n[ NetBSD PCI detection stuff not" |
171 |
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" yet implemented for device '%s' ]\n", |
172 |
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dev->name); |
173 |
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} |
174 |
} |
} |
175 |
return; |
return; |
176 |
} |
} |
222 |
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|
223 |
if (pci_data == NULL) { |
if (pci_data == NULL) { |
224 |
fatal("bus_pci_add(): pci_data == NULL!\n"); |
fatal("bus_pci_add(): pci_data == NULL!\n"); |
225 |
exit(1); |
abort(); |
226 |
} |
} |
227 |
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|
228 |
/* Find the PCI device: */ |
/* Find the PCI device: */ |
339 |
} |
} |
340 |
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341 |
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static void bus_pci_debug_dump__2(struct pci_device *pd) |
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{ |
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if (pd == NULL) |
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return; |
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bus_pci_debug_dump__2(pd->next); |
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debug("bus %3i, dev %2i, func %i: %s\n", |
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pd->bus, pd->device, pd->function, pd->name); |
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} |
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/* |
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* bus_pci_debug_dump(): |
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* |
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* Lists the attached PCI devices (in reverse). |
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*/ |
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void bus_pci_debug_dump(void *extra) |
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{ |
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struct pci_data *d = (struct pci_data *) extra; |
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int iadd = DEBUG_INDENTATION; |
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debug("pci:\n"); |
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debug_indentation(iadd); |
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if (d->first_device == NULL) |
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debug("no devices!\n"); |
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else |
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bus_pci_debug_dump__2(d->first_device); |
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debug_indentation(-iadd); |
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} |
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342 |
/* |
/* |
343 |
* bus_pci_init(): |
* bus_pci_init(): |
344 |
* |
* |
345 |
* This doesn't register a device, but instead returns a pointer to a struct |
* This doesn't register a device, but instead returns a pointer to a struct |
346 |
* which should be passed to other bus_pci functions when accessing the bus. |
* which should be passed to other bus_pci functions when accessing the bus. |
347 |
* |
* |
348 |
* irq_nr is the (optional) IRQ nr that this PCI bus interrupts at. |
* irq_path is the interrupt path to the PCI controller. |
349 |
* |
* |
350 |
* pci_portbase, pci_membase, and pci_irqbase are the port, memory, and |
* pci_portbase, pci_membase, and pci_irqbase are the port, memory, and |
351 |
* interrupt bases for PCI devices (as found in the configuration registers). |
* interrupt bases for PCI devices (as found in the configuration registers). |
356 |
* isa_portbase, isa_membase, and isa_irqbase are the port, memory, and |
* isa_portbase, isa_membase, and isa_irqbase are the port, memory, and |
357 |
* interrupt bases for legacy ISA devices. |
* interrupt bases for legacy ISA devices. |
358 |
*/ |
*/ |
359 |
struct pci_data *bus_pci_init(struct machine *machine, int irq_nr, |
struct pci_data *bus_pci_init(struct machine *machine, char *irq_path, |
360 |
uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, |
uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, |
361 |
uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase, |
uint64_t pci_portbase, uint64_t pci_membase, char *pci_irqbase, |
362 |
uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase) |
uint64_t isa_portbase, uint64_t isa_membase, char *isa_irqbase) |
363 |
{ |
{ |
364 |
struct pci_data *d; |
struct pci_data *d; |
365 |
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|
369 |
exit(1); |
exit(1); |
370 |
} |
} |
371 |
memset(d, 0, sizeof(struct pci_data)); |
memset(d, 0, sizeof(struct pci_data)); |
372 |
d->irq_nr = irq_nr; |
|
373 |
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d->irq_path = strdup(irq_path); |
374 |
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d->irq_path_isa = strdup(isa_irqbase); |
375 |
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d->irq_path_pci = strdup(pci_irqbase); |
376 |
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|
377 |
d->pci_actual_io_offset = pci_actual_io_offset; |
d->pci_actual_io_offset = pci_actual_io_offset; |
378 |
d->pci_actual_mem_offset = pci_actual_mem_offset; |
d->pci_actual_mem_offset = pci_actual_mem_offset; |
379 |
d->pci_portbase = pci_portbase; |
d->pci_portbase = pci_portbase; |
380 |
d->pci_membase = pci_membase; |
d->pci_membase = pci_membase; |
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d->pci_irqbase = pci_irqbase; |
|
381 |
d->isa_portbase = isa_portbase; |
d->isa_portbase = isa_portbase; |
382 |
d->isa_membase = isa_membase; |
d->isa_membase = isa_membase; |
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d->isa_irqbase = isa_irqbase; |
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/* Register the bus: */ |
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machine_bus_register(machine, "pci", bus_pci_debug_dump, d); |
|
383 |
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384 |
/* Assume that the first 64KB could be used by legacy ISA devices: */ |
/* Assume that the first 64KB could be used by legacy ISA devices: */ |
385 |
d->cur_pci_portbase = d->pci_portbase + 0x10000; |
d->cur_pci_portbase = d->pci_portbase + 0x10000; |
402 |
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403 |
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404 |
/* |
/* |
405 |
* Integraphics Systems "igsfb" Framebuffer (graphics) card. |
* Integraphics Systems "igsfb" Framebuffer (graphics) card, used in at |
406 |
* |
* least the NetWinder. |
|
* TODO |
|
407 |
*/ |
*/ |
408 |
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|
409 |
#define PCI_VENDOR_INTEGRAPHICS 0x10ea |
#define PCI_VENDOR_INTEGRAPHICS 0x10ea |
410 |
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|
411 |
PCIINIT(igsfb) |
PCIINIT(igsfb) |
412 |
{ |
{ |
413 |
|
char tmpstr[200]; |
414 |
|
|
415 |
PCI_SET_DATA(PCI_ID_REG, |
PCI_SET_DATA(PCI_ID_REG, |
416 |
PCI_ID_CODE(PCI_VENDOR_INTEGRAPHICS, 0x2010)); |
PCI_ID_CODE(PCI_VENDOR_INTEGRAPHICS, 0x2010)); |
417 |
|
|
422 |
/* TODO */ |
/* TODO */ |
423 |
PCI_SET_DATA(0x10, 0x08000000); |
PCI_SET_DATA(0x10, 0x08000000); |
424 |
|
|
425 |
dev_vga_init(machine, mem, pd->pcibus->isa_membase + 0xa0000, |
snprintf(tmpstr, sizeof(tmpstr), "igsfb addr=0x%llx", |
426 |
0x88800000 + 0x3c0, machine->machine_name); |
(long long)(pd->pcibus->isa_membase + 0x08000000)); |
427 |
|
device_add(machine, tmpstr); |
428 |
} |
} |
429 |
|
|
430 |
|
|
477 |
/* Linux uses these to detect which IRQ the IDE controller uses: */ |
/* Linux uses these to detect which IRQ the IDE controller uses: */ |
478 |
PCI_SET_DATA(0x44, 0x0000000e); |
PCI_SET_DATA(0x44, 0x0000000e); |
479 |
PCI_SET_DATA(0x58, 0x00000003); |
PCI_SET_DATA(0x58, 0x00000003); |
480 |
|
|
481 |
|
switch (machine->machine_type) { |
482 |
|
case MACHINE_CATS: |
483 |
|
bus_isa_init(machine, pd->pcibus->irq_path_isa, |
484 |
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BUS_ISA_PCKBC_FORCE_USE | BUS_ISA_PCKBC_NONPCSTYLE, |
485 |
|
0x7c000000, 0x80000000); |
486 |
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break; |
487 |
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default:fatal("ali_m1543 init: unimplemented machine type\n"); |
488 |
|
exit(1); |
489 |
|
} |
490 |
} |
} |
491 |
|
|
492 |
PCIINIT(ali_m5229) |
PCIINIT(ali_m5229) |
493 |
{ |
{ |
494 |
char tmpstr[300]; |
char tmpstr[300], irqstr[300]; |
495 |
|
|
496 |
PCI_SET_DATA(PCI_ID_REG, |
PCI_SET_DATA(PCI_ID_REG, |
497 |
PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5229)); |
PCI_ID_CODE(PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5229)); |
499 |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
500 |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1); |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1); |
501 |
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|
502 |
|
switch (machine->machine_type) { |
503 |
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case MACHINE_CATS: |
504 |
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/* CATS ISA interrupts are at footbridge irq 10: */ |
505 |
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snprintf(irqstr, sizeof(irqstr), "%s.10.isa", |
506 |
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pd->pcibus->irq_path); |
507 |
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break; |
508 |
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default:fatal("ali_m5229 init: unimplemented machine type\n"); |
509 |
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exit(1); |
510 |
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} |
511 |
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512 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
513 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
514 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i", |
515 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
516 |
pd->pcibus->isa_irqbase + 14); |
irqstr, 14); |
517 |
device_add(machine, tmpstr); |
device_add(machine, tmpstr); |
518 |
} |
} |
519 |
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631 |
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632 |
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633 |
/* |
/* |
634 |
|
* AMD PCnet Ethernet card. |
635 |
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* |
636 |
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* "Am79c970A PCnet-PCI II rev 0" or similar. |
637 |
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*/ |
638 |
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|
639 |
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#define PCI_VENDOR_AMD 0x1022 /* Advanced Micro Devices */ |
640 |
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#define PCI_PRODUCT_AMD_PCNET_PCI 0x2000 /* PCnet-PCI Ethernet */ |
641 |
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|
642 |
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PCIINIT(pcn) |
643 |
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{ |
644 |
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int irq; |
645 |
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|
646 |
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PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_AMD, |
647 |
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PCI_PRODUCT_AMD_PCNET_PCI)); |
648 |
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|
649 |
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PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_NETWORK, |
650 |
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PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x00); /* Revision 0 */ |
651 |
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|
652 |
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switch (machine->machine_type) { |
653 |
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|
654 |
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case MACHINE_EVBMIPS: |
655 |
|
irq = (1 << 8) + 10; /* TODO */ |
656 |
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break; |
657 |
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|
658 |
|
default:fatal("pcn in non-implemented machine type %i\n", |
659 |
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machine->machine_type); |
660 |
|
exit(1); |
661 |
|
} |
662 |
|
|
663 |
|
PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq); |
664 |
|
|
665 |
|
/* |
666 |
|
* TODO: Add the pcn device here. The pcn device will need to work as |
667 |
|
* a wrapper for dev_le + all the DMA magic and whatever is required. |
668 |
|
* It's too much to implement right now. |
669 |
|
*/ |
670 |
|
} |
671 |
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|
672 |
|
|
673 |
|
|
674 |
|
/* |
675 |
* Intel 31244 Serial ATA Controller |
* Intel 31244 Serial ATA Controller |
676 |
* Intel 82371SB PIIX3 PCI-ISA bridge |
* Intel 82371SB PIIX3 PCI-ISA bridge |
677 |
* Intel 82371AB PIIX4 PCI-ISA bridge |
* Intel 82371AB PIIX4 PCI-ISA bridge |
718 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
719 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
720 |
char tmpstr[150]; |
char tmpstr[150]; |
721 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i", |
722 |
(long long)(pd->pcibus->pci_actual_io_offset + 0), |
(long long)(pd->pcibus->pci_actual_io_offset + 0), |
723 |
pd->pcibus->pci_irqbase + 0); |
pd->pcibus->irq_path_pci, irq & 255); |
724 |
device_add(machine, tmpstr); |
device_add(machine, tmpstr); |
725 |
} |
} |
726 |
} |
} |
766 |
PCI_SET_DATA(0x60, 0x0f0e0b0a); |
PCI_SET_DATA(0x60, 0x0f0e0b0a); |
767 |
} |
} |
768 |
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|
769 |
|
struct piix_ide_extra { |
770 |
|
void *wdc0; |
771 |
|
void *wdc1; |
772 |
|
}; |
773 |
|
|
774 |
|
int piix_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value) |
775 |
|
{ |
776 |
|
void *wdc0 = ((struct piix_ide_extra *)pd->extra)->wdc0; |
777 |
|
void *wdc1 = ((struct piix_ide_extra *)pd->extra)->wdc1; |
778 |
|
int enabled = 0; |
779 |
|
|
780 |
|
switch (reg) { |
781 |
|
case PCI_COMMAND_STATUS_REG: |
782 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
783 |
|
enabled = 1; |
784 |
|
if (wdc0 != NULL) |
785 |
|
wdc_set_io_enabled(wdc0, enabled); |
786 |
|
if (wdc1 != NULL) |
787 |
|
wdc_set_io_enabled(wdc1, enabled); |
788 |
|
return 1; |
789 |
|
} |
790 |
|
|
791 |
|
return 0; |
792 |
|
} |
793 |
|
|
794 |
PCIINIT(piix3_ide) |
PCIINIT(piix3_ide) |
795 |
{ |
{ |
796 |
char tmpstr[100]; |
char tmpstr[100]; |
806 |
/* channel 0 and 1 enabled as IDE */ |
/* channel 0 and 1 enabled as IDE */ |
807 |
PCI_SET_DATA(0x40, 0x80008000); |
PCI_SET_DATA(0x40, 0x80008000); |
808 |
|
|
809 |
|
pd->extra = malloc(sizeof(struct piix_ide_extra)); |
810 |
|
if (pd->extra == NULL) { |
811 |
|
fatal("Out of memory.\n"); |
812 |
|
exit(1); |
813 |
|
} |
814 |
|
((struct piix_ide_extra *)pd->extra)->wdc0 = NULL; |
815 |
|
((struct piix_ide_extra *)pd->extra)->wdc1 = NULL; |
816 |
|
|
817 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
818 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
819 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx " |
820 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase + |
821 |
pd->pcibus->isa_irqbase + 14); |
0x1f0), pd->pcibus->irq_path_isa, 14); |
822 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc0 = |
823 |
|
device_add(machine, tmpstr); |
824 |
} |
} |
825 |
|
|
826 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
827 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
828 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx " |
829 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase + |
830 |
pd->pcibus->isa_irqbase + 15); |
0x170), pd->pcibus->irq_path_isa, 15); |
831 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc1 = |
832 |
|
device_add(machine, tmpstr); |
833 |
} |
} |
834 |
|
|
835 |
|
pd->cfg_reg_write = piix_ide_cfg_reg_write; |
836 |
} |
} |
837 |
|
|
838 |
PCIINIT(piix4_ide) |
PCIINIT(piix4_ide) |
850 |
/* channel 0 and 1 enabled as IDE */ |
/* channel 0 and 1 enabled as IDE */ |
851 |
PCI_SET_DATA(0x40, 0x80008000); |
PCI_SET_DATA(0x40, 0x80008000); |
852 |
|
|
853 |
|
pd->extra = malloc(sizeof(struct piix_ide_extra)); |
854 |
|
if (pd->extra == NULL) { |
855 |
|
fatal("Out of memory.\n"); |
856 |
|
exit(1); |
857 |
|
} |
858 |
|
((struct piix_ide_extra *)pd->extra)->wdc0 = NULL; |
859 |
|
((struct piix_ide_extra *)pd->extra)->wdc1 = NULL; |
860 |
|
|
861 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
862 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
863 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
864 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0), |
865 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->irq_path_isa, 14); |
866 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc0 = |
867 |
|
device_add(machine, tmpstr); |
868 |
} |
} |
869 |
|
|
870 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
871 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
872 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
873 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170), |
874 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->irq_path_isa, 15); |
875 |
device_add(machine, tmpstr); |
((struct piix_ide_extra *)pd->extra)->wdc1 = |
876 |
|
device_add(machine, tmpstr); |
877 |
} |
} |
878 |
|
|
879 |
|
pd->cfg_reg_write = piix_ide_cfg_reg_write; |
880 |
} |
} |
881 |
|
|
882 |
|
|
950 |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
951 |
} |
} |
952 |
|
|
953 |
|
struct vt82c586_ide_extra { |
954 |
|
void *wdc0; |
955 |
|
void *wdc1; |
956 |
|
}; |
957 |
|
|
958 |
|
int vt82c586_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value) |
959 |
|
{ |
960 |
|
void *wdc0 = ((struct vt82c586_ide_extra *)pd->extra)->wdc0; |
961 |
|
void *wdc1 = ((struct vt82c586_ide_extra *)pd->extra)->wdc1; |
962 |
|
int enabled = 0; |
963 |
|
|
964 |
|
switch (reg) { |
965 |
|
case PCI_COMMAND_STATUS_REG: |
966 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
967 |
|
enabled = 1; |
968 |
|
if (wdc0 != NULL) |
969 |
|
wdc_set_io_enabled(wdc0, enabled); |
970 |
|
if (wdc1 != NULL) |
971 |
|
wdc_set_io_enabled(wdc1, enabled); |
972 |
|
return 1; |
973 |
|
} |
974 |
|
|
975 |
|
return 0; |
976 |
|
} |
977 |
|
|
978 |
PCIINIT(vt82c586_ide) |
PCIINIT(vt82c586_ide) |
979 |
{ |
{ |
980 |
char tmpstr[100]; |
char tmpstr[100]; |
990 |
/* channel 0 and 1 enabled */ |
/* channel 0 and 1 enabled */ |
991 |
PCI_SET_DATA(0x40, 0x00000003); |
PCI_SET_DATA(0x40, 0x00000003); |
992 |
|
|
993 |
|
pd->extra = malloc(sizeof(struct vt82c586_ide_extra)); |
994 |
|
if (pd->extra == NULL) { |
995 |
|
fatal("Out of memory.\n"); |
996 |
|
exit(1); |
997 |
|
} |
998 |
|
((struct vt82c586_ide_extra *)pd->extra)->wdc0 = NULL; |
999 |
|
((struct vt82c586_ide_extra *)pd->extra)->wdc1 = NULL; |
1000 |
|
|
1001 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
1002 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
1003 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1004 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0), |
1005 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->irq_path_isa, 14); |
1006 |
device_add(machine, tmpstr); |
((struct vt82c586_ide_extra *)pd->extra)->wdc0 = |
1007 |
|
device_add(machine, tmpstr); |
1008 |
} |
} |
1009 |
|
|
1010 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
1011 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
1012 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1013 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170), |
1014 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->irq_path_isa, 15); |
1015 |
device_add(machine, tmpstr); |
((struct vt82c586_ide_extra *)pd->extra)->wdc1 = |
1016 |
|
device_add(machine, tmpstr); |
1017 |
} |
} |
1018 |
|
|
1019 |
|
pd->cfg_reg_write = vt82c586_ide_cfg_reg_write; |
1020 |
} |
} |
1021 |
|
|
1022 |
|
|
1040 |
|
|
1041 |
PCI_SET_DATA(PCI_BHLC_REG, |
PCI_SET_DATA(PCI_BHLC_REG, |
1042 |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
1043 |
|
|
1044 |
|
switch (machine->machine_type) { |
1045 |
|
case MACHINE_NETWINDER: |
1046 |
|
bus_isa_init(machine, pd->pcibus->irq_path_isa, |
1047 |
|
0, 0x7c000000, 0x80000000); |
1048 |
|
break; |
1049 |
|
default:fatal("symphony_83c553 init: unimplemented machine type\n"); |
1050 |
|
exit(1); |
1051 |
|
} |
1052 |
|
} |
1053 |
|
|
1054 |
|
struct symphony_82c105_extra { |
1055 |
|
void *wdc0; |
1056 |
|
void *wdc1; |
1057 |
|
}; |
1058 |
|
|
1059 |
|
int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg, |
1060 |
|
uint32_t value) |
1061 |
|
{ |
1062 |
|
void *wdc0 = ((struct symphony_82c105_extra *)pd->extra)->wdc0; |
1063 |
|
void *wdc1 = ((struct symphony_82c105_extra *)pd->extra)->wdc1; |
1064 |
|
int enabled = 0; |
1065 |
|
|
1066 |
|
printf("reg = 0x%x\n", reg); |
1067 |
|
switch (reg) { |
1068 |
|
case PCI_COMMAND_STATUS_REG: |
1069 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
1070 |
|
enabled = 1; |
1071 |
|
printf(" value = 0x%"PRIx32"\n", value); |
1072 |
|
if (wdc0 != NULL) |
1073 |
|
wdc_set_io_enabled(wdc0, enabled); |
1074 |
|
if (wdc1 != NULL) |
1075 |
|
wdc_set_io_enabled(wdc1, enabled); |
1076 |
|
/* Set all bits: */ |
1077 |
|
PCI_SET_DATA(reg, value); |
1078 |
|
return 1; |
1079 |
|
case PCI_MAPREG_START: |
1080 |
|
case PCI_MAPREG_START + 4: |
1081 |
|
case PCI_MAPREG_START + 8: |
1082 |
|
case PCI_MAPREG_START + 12: |
1083 |
|
case PCI_MAPREG_START + 16: |
1084 |
|
case PCI_MAPREG_START + 20: |
1085 |
|
PCI_SET_DATA(reg, value); |
1086 |
|
return 1; |
1087 |
|
} |
1088 |
|
|
1089 |
|
return 0; |
1090 |
} |
} |
1091 |
|
|
1092 |
PCIINIT(symphony_82c105) |
PCIINIT(symphony_82c105) |
1100 |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
1101 |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05); |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05); |
1102 |
|
|
1103 |
|
/* TODO: Interrupt line: */ |
1104 |
|
/* PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000); */ |
1105 |
|
|
1106 |
/* APO_IDECONF */ |
/* APO_IDECONF */ |
1107 |
/* channel 0 and 1 enabled */ |
/* channel 0 and 1 enabled */ |
1108 |
PCI_SET_DATA(0x40, 0x00000003); |
PCI_SET_DATA(0x40, 0x00000003); |
1109 |
|
|
1110 |
|
pd->extra = malloc(sizeof(struct symphony_82c105_extra)); |
1111 |
|
if (pd->extra == NULL) { |
1112 |
|
fatal("Out of memory.\n"); |
1113 |
|
exit(1); |
1114 |
|
} |
1115 |
|
((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL; |
1116 |
|
((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL; |
1117 |
|
|
1118 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
1119 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
1120 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1121 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0), |
1122 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->irq_path_isa, 14); |
1123 |
device_add(machine, tmpstr); |
((struct symphony_82c105_extra *)pd->extra)->wdc0 = |
1124 |
|
device_add(machine, tmpstr); |
1125 |
} |
} |
1126 |
|
|
1127 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
1128 |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 3, DISKIMAGE_IDE)) { |
1129 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s." |
1130 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
"isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170), |
1131 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->irq_path_isa, 15); |
1132 |
device_add(machine, tmpstr); |
((struct symphony_82c105_extra *)pd->extra)->wdc1 = |
1133 |
|
device_add(machine, tmpstr); |
1134 |
} |
} |
1135 |
|
|
1136 |
|
pd->cfg_reg_write = symphony_82c105_cfg_reg_write; |
1137 |
} |
} |
1138 |
|
|
1139 |
|
|
1148 |
PCIINIT(dec21143) |
PCIINIT(dec21143) |
1149 |
{ |
{ |
1150 |
uint64_t port, memaddr; |
uint64_t port, memaddr; |
1151 |
int irq = 0; /* TODO */ |
int pci_int_line = 0x101, irq = 0, isa = 0; |
1152 |
int pci_int_line = 0x101; |
char irqstr[200]; |
1153 |
char tmpstr[200]; |
char tmpstr[200]; |
1154 |
|
|
1155 |
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC, |
PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC, |
1173 |
irq = 8 + 7; |
irq = 8 + 7; |
1174 |
pci_int_line = 0x407; |
pci_int_line = 0x407; |
1175 |
break; |
break; |
|
case MACHINE_ALGOR: |
|
|
/* TODO */ |
|
|
irq = 8 + 7; |
|
|
pci_int_line = 0x407; |
|
|
break; |
|
1176 |
case MACHINE_PREP: |
case MACHINE_PREP: |
1177 |
irq = 32 + 10; |
irq = 10; |
1178 |
|
isa = 1; |
1179 |
pci_int_line = 0x20a; |
pci_int_line = 0x20a; |
1180 |
break; |
break; |
1181 |
case MACHINE_MVMEPPC: |
case MACHINE_MVMEPPC: |
1182 |
/* TODO */ |
/* TODO */ |
1183 |
irq = 32 + 10; |
irq = 10; |
1184 |
pci_int_line = 0x40a; |
pci_int_line = 0x40a; |
1185 |
break; |
break; |
1186 |
case MACHINE_PMPPC: |
case MACHINE_PMPPC: |
1199 |
|
|
1200 |
allocate_device_space(pd, 0x100, 0x100, &port, &memaddr); |
allocate_device_space(pd, 0x100, 0x100, &port, &memaddr); |
1201 |
|
|
1202 |
|
if (isa) |
1203 |
|
snprintf(irqstr, sizeof(irqstr), "%s.isa.%i", |
1204 |
|
pd->pcibus->irq_path_isa, irq); |
1205 |
|
else |
1206 |
|
snprintf(irqstr, sizeof(irqstr), "%s.%i", |
1207 |
|
pd->pcibus->irq_path_pci, irq); |
1208 |
|
|
1209 |
snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx " |
snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx " |
1210 |
"irq=%i pci_little_endian=1", (long long)port, (long long)memaddr, |
"irq=%s pci_little_endian=1", (long long)port, |
1211 |
irq); |
(long long)memaddr, irqstr); |
1212 |
|
|
1213 |
device_add(machine, tmpstr); |
device_add(machine, tmpstr); |
1214 |
} |
} |
1215 |
|
|