25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: bus_pci.c,v 1.70 2006/08/12 19:38:24 debug Exp $ |
* $Id: bus_pci.c,v 1.72 2006/10/08 02:28:58 debug Exp $ |
29 |
* |
* |
30 |
* Generic PCI bus framework. This is not a normal "device", but is used by |
* Generic PCI bus framework. This is not a normal "device", but is used by |
31 |
* individual PCI controllers and devices. |
* individual PCI controllers and devices. |
1054 |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0)); |
1055 |
} |
} |
1056 |
|
|
1057 |
|
struct symphony_82c105_extra { |
1058 |
|
void *wdc0; |
1059 |
|
void *wdc1; |
1060 |
|
}; |
1061 |
|
|
1062 |
|
int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg, |
1063 |
|
uint32_t value) |
1064 |
|
{ |
1065 |
|
void *wdc0 = ((struct symphony_82c105_extra *)pd->extra)->wdc0; |
1066 |
|
void *wdc1 = ((struct symphony_82c105_extra *)pd->extra)->wdc1; |
1067 |
|
int enabled = 0; |
1068 |
|
|
1069 |
|
printf("reg = 0x%x\n", reg); |
1070 |
|
switch (reg) { |
1071 |
|
case PCI_COMMAND_STATUS_REG: |
1072 |
|
if (value & PCI_COMMAND_IO_ENABLE) |
1073 |
|
enabled = 1; |
1074 |
|
printf(" value = 0x%"PRIx32"\n", value); |
1075 |
|
if (wdc0 != NULL) |
1076 |
|
wdc_set_io_enabled(wdc0, enabled); |
1077 |
|
if (wdc1 != NULL) |
1078 |
|
wdc_set_io_enabled(wdc1, enabled); |
1079 |
|
/* Set all bits: */ |
1080 |
|
PCI_SET_DATA(reg, value); |
1081 |
|
return 1; |
1082 |
|
case PCI_MAPREG_START: |
1083 |
|
case PCI_MAPREG_START + 4: |
1084 |
|
case PCI_MAPREG_START + 8: |
1085 |
|
case PCI_MAPREG_START + 12: |
1086 |
|
case PCI_MAPREG_START + 16: |
1087 |
|
case PCI_MAPREG_START + 20: |
1088 |
|
PCI_SET_DATA(reg, value); |
1089 |
|
return 1; |
1090 |
|
} |
1091 |
|
|
1092 |
|
return 0; |
1093 |
|
} |
1094 |
|
|
1095 |
PCIINIT(symphony_82c105) |
PCIINIT(symphony_82c105) |
1096 |
{ |
{ |
1097 |
char tmpstr[100]; |
char tmpstr[100]; |
1103 |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
PCI_SET_DATA(PCI_CLASS_REG, PCI_CLASS_CODE(PCI_CLASS_MASS_STORAGE, |
1104 |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05); |
PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05); |
1105 |
|
|
1106 |
|
/* TODO: Interrupt line: */ |
1107 |
|
/* PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000); */ |
1108 |
|
|
1109 |
/* APO_IDECONF */ |
/* APO_IDECONF */ |
1110 |
/* channel 0 and 1 enabled */ |
/* channel 0 and 1 enabled */ |
1111 |
PCI_SET_DATA(0x40, 0x00000003); |
PCI_SET_DATA(0x40, 0x00000003); |
1112 |
|
|
1113 |
|
pd->extra = malloc(sizeof(struct symphony_82c105_extra)); |
1114 |
|
if (pd->extra == NULL) { |
1115 |
|
fatal("Out of memory.\n"); |
1116 |
|
exit(1); |
1117 |
|
} |
1118 |
|
((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL; |
1119 |
|
((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL; |
1120 |
|
|
1121 |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 0, DISKIMAGE_IDE) || |
1122 |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
diskimage_exist(machine, 1, DISKIMAGE_IDE)) { |
1123 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
1124 |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
(long long)(pd->pcibus->isa_portbase + 0x1f0), |
1125 |
pd->pcibus->isa_irqbase + 14); |
pd->pcibus->isa_irqbase + 14); |
1126 |
device_add(machine, tmpstr); |
((struct symphony_82c105_extra *)pd->extra)->wdc0 = |
1127 |
|
device_add(machine, tmpstr); |
1128 |
} |
} |
1129 |
|
|
1130 |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
if (diskimage_exist(machine, 2, DISKIMAGE_IDE) || |
1132 |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%i", |
1133 |
(long long)(pd->pcibus->isa_portbase + 0x170), |
(long long)(pd->pcibus->isa_portbase + 0x170), |
1134 |
pd->pcibus->isa_irqbase + 15); |
pd->pcibus->isa_irqbase + 15); |
1135 |
device_add(machine, tmpstr); |
((struct symphony_82c105_extra *)pd->extra)->wdc1 = |
1136 |
|
device_add(machine, tmpstr); |
1137 |
} |
} |
1138 |
|
|
1139 |
|
pd->cfg_reg_write = symphony_82c105_cfg_reg_write; |
1140 |
} |
} |
1141 |
|
|
1142 |
|
|