25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_mips_v2p.c,v 1.2 2005/11/11 13:23:16 debug Exp $ |
* $Id: memory_mips_v2p.c,v 1.3 2005/12/26 12:32:10 debug Exp $ |
29 |
* |
* |
30 |
* Included from memory.c. |
* Included from memory.c. |
31 |
*/ |
*/ |
280 |
|
|
281 |
if (use_tlb) { |
if (use_tlb) { |
282 |
#ifndef V2P_MMU3K |
#ifndef V2P_MMU3K |
283 |
int odd = 0, cached_lo1 = 0; |
int odd = 0; |
284 |
|
uint64_t cached_lo1 = 0; |
285 |
#endif |
#endif |
286 |
int g_bit, v_bit, d_bit; |
int g_bit, v_bit, d_bit; |
287 |
uint64_t cached_hi, cached_lo0; |
uint64_t cached_hi, cached_lo0; |