--- trunk/src/cpus/memory_mips_v2p.c	2007/10/08 16:19:37	22
+++ trunk/src/cpus/memory_mips_v2p.c	2007/10/08 16:19:56	24
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: memory_mips_v2p.c,v 1.3 2005/12/26 12:32:10 debug Exp $
+ *  $Id: memory_mips_v2p.c,v 1.5 2006/06/16 18:31:26 debug Exp $
  *
  *  Included from memory.c.
  */
@@ -48,12 +48,10 @@
 {
 	int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ;
 	int no_exceptions = flags & FLAG_NOEXCEPTIONS;
-	int instr = flags & FLAG_INSTR;
 	int ksu, use_tlb, status, i;
 	uint64_t vaddr_vpn2=0, vaddr_asid=0;
 	int exccode, tlb_refill;
 	struct mips_coproc *cp0;
-	int bintrans_cached = cpu->machine->bintrans_enable;
 
 #ifdef V2P_MMU3K
 	const int x_64 = 0;
@@ -85,51 +83,6 @@
 #endif	/*  !V2P_MMU3K  */
 
 
-#ifdef USE_TINY_CACHE
-	/*
-	 *  Check the tiny translation cache first:
-	 *
-	 *  Only userland addresses are checked, because other addresses
-	 *  are probably better of being statically translated, or through
-	 *  the TLB.  (Note: When running with 64-bit addresses, this
-	 *  will still produce the correct result. At worst, we check the
-	 *  cache in vain, but the result should still be correct.)
-	 */
-	if (!bintrans_cached &&
-	    (vaddr & 0xc0000000ULL) != 0x80000000ULL) {
-		int i, wf = 1 + (writeflag == MEM_WRITE);
-		uint64_t vaddr_shift_12 = vaddr >> 12;
-
-		if (instr) {
-			/*  Code:  */
-			for (i=0; i<N_TRANSLATION_CACHE_INSTR; i++) {
-				if (cpu->cd.mips.translation_cache_instr[i].wf
-				    >= wf && vaddr_shift_12 == (cpu->cd.mips.
-				    translation_cache_instr[i].vaddr_pfn)) {
-					*return_addr = cpu->cd.mips.
-					    translation_cache_instr[i].paddr
-					    | (vaddr & 0xfff);
-					return cpu->cd.mips.
-					    translation_cache_instr[i].wf;
-				}
-			}
-		} else {
-			/*  Data:  */
-			for (i=0; i<N_TRANSLATION_CACHE_DATA; i++) {
-				if (cpu->cd.mips.translation_cache_data[i].wf
-				    >= wf && vaddr_shift_12 == (cpu->cd.mips.
-				    translation_cache_data[i].vaddr_pfn)) {
-					*return_addr = cpu->cd.mips.
-					    translation_cache_data[i].paddr
-					    | (vaddr & 0xfff);
-					return cpu->cd.mips.
-					    translation_cache_data[i].wf;
-				}
-			}
-		}
-	}
-#endif
-
 	exccode = -1;
 	tlb_refill = 1;
 
@@ -379,24 +332,26 @@
 			/*  Is there a VPN and ASID match?  */
 			if (entry_vpn2 == vaddr_vpn2 &&
 			    (entry_asid == vaddr_asid || g_bit)) {
-				/*  debug("OK MAP 1, i=%i { vaddr=%016llx "
-				    "==> paddr %016llx v=%i d=%i "
-				    "asid=0x%02x }\n", i, (long long)vaddr,
-				    (long long) *return_addr, v_bit?1:0,
+				/*  debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" "
+				    "==> paddr %016"PRIx64" v=%i d=%i "
+				    "asid=0x%02x }\n", i, (uint64_t) vaddr,
+				    (uint64_t) *return_addr, v_bit?1:0,
 				    d_bit?1:0, vaddr_asid);  */
 				if (v_bit) {
 					if (d_bit || (!d_bit &&
 					    writeflag == MEM_READ)) {
 						uint64_t paddr;
 						/*  debug("OK MAP 2!!! { w=%i "
-						    "vaddr=%016llx ==> d=%i v="
-						    "%i paddr %016llx ",
-						    writeflag, (long long)vaddr,
+						    "vaddr=%016"PRIx64" ==> "
+						    "d=%i v=%i paddr %016"
+						    PRIx64" ",
+						    writeflag, (uint64_t)vaddr,
 						    d_bit?1:0, v_bit?1:0,
-						    (long long) *return_addr);
+						    (uint64_t) *return_addr);
 						    debug(", tlb entry %2i: ma"
-						    "sk=%016llx hi=%016llx lo0"
-						    "=%016llx lo1=%016llx\n",
+						    "sk=%016"PRIx64" hi=%016"
+						    PRIx64" lo0=%016"PRIx64
+						    " lo1=%016"PRIx64"\n",
 						    i, cp0->tlbs[i].mask, cp0->
 						    tlbs[i].hi, cp0->tlbs[i].
 						    lo0, cp0->tlbs[i].lo1);
@@ -414,18 +369,6 @@
 						    (vaddr & pmask);
 #endif
 
-						/*
-						 *  Enter into the tiny trans-
-						 *  lation cache (if enabled)
-						 *  and return:
-						 */
-						if (!bintrans_cached)
-							insert_into_tiny_cache(
-							    cpu, instr, d_bit?
-							    MEM_WRITE :
-							    MEM_READ,
-							    vaddr, paddr);
-
 						*return_addr = paddr;
 						return d_bit? 2 : 1;
 					} else {