25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc.c,v 1.34 2006/07/16 13:32:26 debug Exp $ |
* $Id: cpu_sparc.c,v 1.38 2006/09/19 10:50:08 debug Exp $ |
29 |
* |
* |
30 |
* SPARC CPU emulation. |
* SPARC CPU emulation. |
31 |
*/ |
*/ |
39 |
#include "machine.h" |
#include "machine.h" |
40 |
#include "memory.h" |
#include "memory.h" |
41 |
#include "misc.h" |
#include "misc.h" |
42 |
|
#include "settings.h" |
43 |
#include "symbol.h" |
#include "symbol.h" |
44 |
|
|
45 |
|
|
91 |
|
|
92 |
cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot; |
cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot; |
93 |
|
|
94 |
|
/* TODO: Separate this into 64-bit vs 32-bit? */ |
95 |
|
cpu->translate_v2p = sparc_translate_v2p; |
96 |
|
|
97 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
98 |
cpu->run_instr = sparc32_run_instr; |
cpu->run_instr = sparc32_run_instr; |
99 |
cpu->update_translation_table = |
cpu->update_translation_table = |
151 |
exit(1); |
exit(1); |
152 |
} |
} |
153 |
|
|
154 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
155 |
|
CPU_SETTINGS_ADD_REGISTER64("y", cpu->cd.sparc.y); |
156 |
|
CPU_SETTINGS_ADD_REGISTER64("pstate", cpu->cd.sparc.pstate); |
157 |
|
for (i=0; i<N_SPARC_REG; i++) |
158 |
|
CPU_SETTINGS_ADD_REGISTER64(sparc_regnames[i], |
159 |
|
cpu->cd.sparc.r[i]); |
160 |
|
/* TODO: Handler for writes to the zero register! */ |
161 |
|
|
162 |
return 1; |
return 1; |
163 |
} |
} |
164 |
|
|
291 |
|
|
292 |
|
|
293 |
/* |
/* |
|
* sparc_cpu_register_match(): |
|
|
*/ |
|
|
void sparc_cpu_register_match(struct machine *m, char *name, |
|
|
int writeflag, uint64_t *valuep, int *match_register) |
|
|
{ |
|
|
int i, cpunr = 0; |
|
|
|
|
|
/* CPU number: */ |
|
|
/* TODO */ |
|
|
|
|
|
for (i=0; i<N_SPARC_REG; i++) { |
|
|
if (strcasecmp(name, sparc_regnames[i]) == 0) { |
|
|
if (writeflag && i != SPARC_ZEROREG) |
|
|
m->cpus[cpunr]->cd.sparc.r[i] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.sparc.r[i]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
|
|
|
|
if (strcasecmp(name, "pc") == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else { |
|
|
*valuep = m->cpus[cpunr]->pc; |
|
|
} |
|
|
*match_register = 1; |
|
|
} |
|
|
|
|
|
if (strcasecmp(name, "y") == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.sparc.y = (uint32_t) *valuep; |
|
|
} else { |
|
|
*valuep = (uint32_t) m->cpus[cpunr]->cd.sparc.y; |
|
|
} |
|
|
*match_register = 1; |
|
|
} |
|
|
|
|
|
if (*match_register && m->cpus[cpunr]->is_32bit) |
|
|
(*valuep) &= 0xffffffffULL; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
294 |
* sparc_cpu_tlbdump(): |
* sparc_cpu_tlbdump(): |
295 |
* |
* |
296 |
* Called from the debugger to dump the TLB in a readable format. |
* Called from the debugger to dump the TLB in a readable format. |
440 |
switch (op2) { |
switch (op2) { |
441 |
case 56:/* jump and link */ |
case 56:/* jump and link */ |
442 |
return 1; |
return 1; |
443 |
|
case 57:/* return */ |
444 |
|
return 1; |
445 |
} |
} |
446 |
break; |
break; |
447 |
} |
} |
645 |
case 41:rs_name = "psr"; |
case 41:rs_name = "psr"; |
646 |
no_rs2 = 1; |
no_rs2 = 1; |
647 |
break; |
break; |
648 |
case 42:rs_name = "wim"; |
case 42:/* TODO: something with wim only, on sparc v8? */ |
649 |
|
rs_name = sparc_pregnames[rs1]; |
650 |
no_rs2 = 1; |
no_rs2 = 1; |
651 |
break; |
break; |
652 |
case 43:/* ? */ |
case 43:/* ? */ |