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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_sh_instr.c,v 1.9 2006/07/25 21:29:04 debug Exp $ |
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* |
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* SH instructions. |
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* |
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* Individual functions should keep track of cpu->n_translated_instrs. |
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* (If no instruction was executed, then it should be decreased. If, say, 4 |
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* instructions were combined into one function and executed, then it should |
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* be increased by 3.) |
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*/ |
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|
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|
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/* |
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* nop: Nothing |
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*/ |
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X(nop) |
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{ |
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} |
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|
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|
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/* |
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* mov_rm_rn: Copy rm into rn |
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* |
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* arg[0] = ptr to rm |
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* arg[1] = ptr to rn |
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*/ |
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X(mov_rm_rn) |
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{ |
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reg(ic->arg[1]) = reg(ic->arg[0]); |
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} |
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|
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|
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/* |
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* mov_imm_rn: Set rn to an signed 8-bit value |
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* |
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* arg[0] = int8_t imm, extended to at least int32_t |
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* arg[1] = ptr to rn |
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*/ |
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X(mov_imm_rn) |
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{ |
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reg(ic->arg[1]) = (int32_t)ic->arg[0]; |
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} |
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|
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|
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/* |
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* mov_l_disp_pc_rn: Set rn to an immediate value relative to the current pc |
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* |
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* arg[0] = offset from beginning of the current pc's page |
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* arg[1] = ptr to rn |
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*/ |
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X(mov_l_disp_pc_rn) |
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{ |
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reg(ic->arg[1]) = ic->arg[0] + (cpu->pc & |
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~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT)); |
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} |
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|
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|
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/* |
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* or_rm_rn: rn = rn or rm |
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* |
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* arg[0] = ptr to rm |
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* arg[1] = ptr to rn |
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*/ |
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X(or_rm_rn) |
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{ |
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reg(ic->arg[1]) |= reg(ic->arg[0]); |
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} |
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|
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|
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/* |
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* shll_rn: Shift rn left by 1 |
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* |
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* arg[0] = ptr to rn |
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*/ |
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X(shll_rn) |
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{ |
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uint32_t rn = reg(ic->arg[0]); |
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if (rn >> 31) |
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cpu->cd.sh.sr |= SH_SR_T; |
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else |
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cpu->cd.sh.sr &= ~SH_SR_T; |
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reg(ic->arg[0]) = rn << 1; |
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} |
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|
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|
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/* |
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* stc_sr_rn: Store SR into Rn |
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* |
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* arg[0] = ptr to rn |
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*/ |
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X(stc_sr_rn) |
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{ |
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if (!(cpu->cd.sh.sr & SH_SR_MD)) { |
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fatal("TODO: Throw RESINST exception, if MD = 0.\n"); |
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exit(1); |
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} |
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|
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reg(ic->arg[0]) = cpu->cd.sh.sr; |
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} |
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|
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|
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/* |
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* ldc_rm_sr: Store Rm into SR |
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* |
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* arg[0] = ptr to rm |
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*/ |
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X(ldc_rm_sr) |
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{ |
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if (!(cpu->cd.sh.sr & SH_SR_MD)) { |
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fatal("TODO: Throw RESINST exception, if MD = 0.\n"); |
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exit(1); |
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} |
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|
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sh_update_sr(cpu, reg(ic->arg[0])); |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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X(end_of_page) |
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{ |
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/* Update the PC: (offset 0, but on the next page) */ |
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cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) << |
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SH_INSTR_ALIGNMENT_SHIFT); |
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cpu->pc += (SH_IC_ENTRIES_PER_PAGE << |
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SH_INSTR_ALIGNMENT_SHIFT); |
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|
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/* Find the new physical page and update the translation pointers: */ |
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DYNTRANS_PC_TO_POINTERS(cpu); |
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|
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/* end_of_page doesn't count as an executed instruction: */ |
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cpu->n_translated_instrs --; |
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} |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* sh_instr_to_be_translated(): |
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* |
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* Translate an instruction word into an sh_instr_call. ic is filled in with |
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* valid data for the translated instruction, or a "nothing" instruction if |
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* there was a translation failure. The newly translated instruction is then |
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* executed. |
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*/ |
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X(to_be_translated) |
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{ |
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uint64_t addr, low_pc; |
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uint32_t iword; |
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unsigned char *page; |
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unsigned char ib[4]; |
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int main_opcode, isize = cpu->cd.sh.compact? 2 : sizeof(ib); |
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int in_crosspage_delayslot = 0, r8, r4, lo4, lo8; |
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/* void (*samepage_function)(struct cpu *, struct sh_instr_call *); */ |
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|
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/* Figure out the (virtual) address of the instruction: */ |
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low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page) |
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/ sizeof(struct sh_instr_call); |
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|
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/* Special case for branch with delayslot on the next page: */ |
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if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) { |
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/* fatal("[ delay-slot translation across page " |
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"boundary ]\n"); */ |
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in_crosspage_delayslot = 1; |
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} |
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|
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addr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1) |
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<< SH_INSTR_ALIGNMENT_SHIFT); |
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addr += (low_pc << SH_INSTR_ALIGNMENT_SHIFT); |
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cpu->pc = (MODE_int_t)addr; |
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addr &= ~((1 << SH_INSTR_ALIGNMENT_SHIFT) - 1); |
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|
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/* Read the instruction word from memory: */ |
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#ifdef MODE32 |
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page = cpu->cd.sh.host_load[(uint32_t)addr >> 12]; |
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#else |
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{ |
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const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
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const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
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const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
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uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1; |
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uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
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uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N- |
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DYNTRANS_L3N)) & mask3; |
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struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.sh.l1_64[x1]; |
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struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2]; |
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page = l3->host_load[x3]; |
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} |
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#endif |
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|
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if (page != NULL) { |
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/* fatal("TRANSLATION HIT!\n"); */ |
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memcpy(ib, page + (addr & 0xfff), isize); |
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} else { |
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/* fatal("TRANSLATION MISS!\n"); */ |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, ib, |
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isize, MEM_READ, CACHE_INSTRUCTION)) { |
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fatal("to_be_translated(): read failed: TODO\n"); |
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goto bad; |
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} |
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} |
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|
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iword = *((uint32_t *)&ib[0]); |
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|
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if (cpu->cd.sh.compact) { |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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iword = LE16_TO_HOST(iword); |
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else |
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iword = BE16_TO_HOST(iword); |
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main_opcode = iword >> 12; |
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r8 = (iword >> 8) & 0xf; |
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r4 = (iword >> 4) & 0xf; |
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lo8 = iword & 0xff; |
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lo4 = iword & 0xf; |
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} else { |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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iword = LE32_TO_HOST(iword); |
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else |
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iword = BE32_TO_HOST(iword); |
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main_opcode = -1; /* TODO */ |
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fatal("SH5/SH64 isn't implemented yet. Sorry.\n"); |
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goto bad; |
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} |
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|
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|
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#define DYNTRANS_TO_BE_TRANSLATED_HEAD |
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#include "cpu_dyntrans.c" |
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#undef DYNTRANS_TO_BE_TRANSLATED_HEAD |
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|
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|
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/* |
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* Translate the instruction: |
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*/ |
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|
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switch (main_opcode) { |
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|
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case 0x0: |
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switch (lo8) { |
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case 0x02: /* STC SR,Rn */ |
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ic->f = instr(stc_sr_rn); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */ |
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break; |
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case 0x09: /* NOP */ |
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ic->f = instr(nop); |
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if (iword & 0x0f00) { |
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fatal("Unimplemented NOP variant?\n"); |
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goto bad; |
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} |
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break; |
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default:fatal("Unimplemented opcode 0x%x,0x03%x\n", |
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main_opcode, iword & 0xfff); |
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goto bad; |
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} |
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break; |
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|
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case 0x2: |
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switch (lo4) { |
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case 0xb: /* OR Rm,Rn */ |
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ic->f = instr(or_rm_rn); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */ |
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ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */ |
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break; |
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default:fatal("Unimplemented opcode 0x%x,0x%x\n", |
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main_opcode, lo4); |
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goto bad; |
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} |
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break; |
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|
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case 0x4: |
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switch (lo8) { |
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case 0x00: /* SHLL Rn */ |
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ic->f = instr(shll_rn); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */ |
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break; |
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case 0x0e: /* LDC Rm,SR */ |
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ic->f = instr(ldc_rm_sr); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* m */ |
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break; |
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default:fatal("Unimplemented opcode 0x%x,0x02%x\n", |
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main_opcode, lo8); |
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goto bad; |
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} |
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break; |
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|
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case 0x6: |
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switch (lo4) { |
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case 0x3: /* MOV Rm,Rn */ |
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ic->f = instr(mov_rm_rn); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */ |
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ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */ |
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break; |
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default:fatal("Unimplemented opcode 0x%x,0x%x\n", |
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main_opcode, lo4); |
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goto bad; |
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} |
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break; |
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|
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case 0xd: /* MOV.L @(disp,PC),Rn */ |
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ic->f = instr(mov_l_disp_pc_rn); |
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ic->arg[0] = lo8 * 4 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1) |
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<< SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4; |
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ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */ |
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break; |
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|
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case 0xe: /* MOV #imm,Rn */ |
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ic->f = instr(mov_imm_rn); |
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ic->arg[0] = (int8_t)lo8; |
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ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */ |
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break; |
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|
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default:fatal("Unimplemented main opcode 0x%x\n", main_opcode); |
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goto bad; |
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} |
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|
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|
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#define DYNTRANS_TO_BE_TRANSLATED_TAIL |
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#include "cpu_dyntrans.c" |
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#undef DYNTRANS_TO_BE_TRANSLATED_TAIL |
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} |
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|