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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_sh_instr.c,v 1.44 2006/11/02 05:43:43 debug Exp $ |
* $Id: cpu_sh_instr.c,v 1.49 2007/01/28 16:59:06 debug Exp $ |
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* |
* |
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* SH instructions. |
* SH instructions. |
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* |
* |
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/* |
/* |
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* xor_b_imm_r0_gbr: mem[r0+gbr] |= imm |
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* or_b_imm_r0_gbr: mem[r0+gbr] ^= imm |
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* and_b_imm_r0_gbr: mem[r0+gbr] &= imm |
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* |
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* arg[0] = imm |
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*/ |
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X(xor_b_imm_r0_gbr) |
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{ |
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uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0]; |
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uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12]; |
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if (p != NULL) { |
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p[addr & 0xfff] ^= ic->arg[0]; |
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} else { |
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uint8_t data; |
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SYNCH_PC; |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data, |
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sizeof(data), MEM_READ, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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data ^= ic->arg[0]; |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data, |
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sizeof(data), MEM_WRITE, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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} |
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} |
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X(or_b_imm_r0_gbr) |
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{ |
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uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0]; |
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uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12]; |
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if (p != NULL) { |
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p[addr & 0xfff] |= ic->arg[0]; |
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} else { |
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uint8_t data; |
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SYNCH_PC; |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data, |
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sizeof(data), MEM_READ, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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data |= ic->arg[0]; |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data, |
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sizeof(data), MEM_WRITE, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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} |
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} |
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X(and_b_imm_r0_gbr) |
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{ |
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uint32_t addr = cpu->cd.sh.gbr + cpu->cd.sh.r[0]; |
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uint8_t *p = (uint8_t *) cpu->cd.sh.host_store[addr >> 12]; |
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if (p != NULL) { |
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p[addr & 0xfff] &= ic->arg[0]; |
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} else { |
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uint8_t data; |
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SYNCH_PC; |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data, |
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sizeof(data), MEM_READ, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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data &= ic->arg[0]; |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, (unsigned char *)&data, |
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sizeof(data), MEM_WRITE, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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} |
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} |
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/* |
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* mov_imm_rn: Set rn to a signed 8-bit value |
* mov_imm_rn: Set rn to a signed 8-bit value |
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* add_imm_rn: Add a signed 8-bit value to Rn |
* add_imm_rn: Add a signed 8-bit value to Rn |
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* |
* |
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cpu->cd.sh.utlb_hi[urc] = cpu->cd.sh.pteh; |
cpu->cd.sh.utlb_hi[urc] = cpu->cd.sh.pteh; |
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cpu->cd.sh.utlb_lo[urc] = cpu->cd.sh.ptel; |
cpu->cd.sh.utlb_lo[urc] = cpu->cd.sh.ptel; |
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if ((old_lo & SH4_PTEL_SZ_MASK) == SH4_PTEL_SZ_4K) |
/* Invalidate the old mapping, if it belonged to the same ASID: */ |
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cpu->invalidate_translation_caches(cpu, |
if ((old_hi & SH4_PTEH_ASID_MASK) == |
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old_hi & 0xfffff000, INVALIDATE_VADDR); |
(cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) { |
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else |
if ((old_lo & SH4_PTEL_SZ_MASK) == SH4_PTEL_SZ_4K) |
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cpu->invalidate_translation_caches(cpu, |
cpu->invalidate_translation_caches(cpu, |
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old_hi & 0xfffff000, INVALIDATE_ALL); |
old_hi & 0xfffff000, INVALIDATE_VADDR); |
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else |
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cpu->invalidate_translation_caches(cpu, |
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old_hi & 0xfffff000, INVALIDATE_ALL); |
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} |
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} |
} |
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/* STC Rm_BANK, Rn */ |
/* STC Rm_BANK, Rn */ |
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ic->f = instr(copy_privileged_register); |
ic->f = instr(copy_privileged_register); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7]; |
ic->arg[0] = (size_t)&cpu->cd.sh.r_bank[(lo8 >> 4) & 7]; |
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} else if (iword == 0x00ff) { |
} else if (iword == SH_INVALID_INSTR) { |
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/* PROM emulation specifically for Dreamcast */ |
/* PROM emulation specifically for Dreamcast */ |
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ic->f = instr(prom_emul_dreamcast); |
ic->f = instr(prom_emul_dreamcast); |
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} else { |
} else { |
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case 0x1b: /* TAS.B @Rn */ |
case 0x1b: /* TAS.B @Rn */ |
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ic->f = instr(tas_b_rn); |
ic->f = instr(tas_b_rn); |
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break; |
break; |
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case 0x1e: /* LDC Rm,GBR */ |
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ic->f = instr(mov_rm_rn); |
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ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* m */ |
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ic->arg[1] = (size_t)&cpu->cd.sh.gbr; |
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break; |
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case 0x20: /* SHAL Rn */ |
case 0x20: /* SHAL Rn */ |
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ic->f = instr(shll_rn); /* NOTE: shll */ |
ic->f = instr(shll_rn); /* NOTE: shll */ |
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break; |
break; |
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ic->f = instr(or_imm_r0); |
ic->f = instr(or_imm_r0); |
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ic->arg[0] = lo8; |
ic->arg[0] = lo8; |
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break; |
break; |
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case 0xd: /* AND.B #imm,@(R0,GBR) */ |
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ic->f = instr(and_b_imm_r0_gbr); |
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ic->arg[0] = lo8; |
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break; |
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case 0xe: /* XOR.B #imm,@(R0,GBR) */ |
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ic->f = instr(xor_b_imm_r0_gbr); |
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ic->arg[0] = lo8; |
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break; |
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case 0xf: /* OR.B #imm,@(R0,GBR) */ |
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ic->f = instr(or_b_imm_r0_gbr); |
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ic->arg[0] = lo8; |
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break; |
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default:fatal("Unimplemented opcode 0x%x,0x%x\n", |
default:fatal("Unimplemented opcode 0x%x,0x%x\n", |
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main_opcode, r8); |
main_opcode, r8); |
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goto bad; |
goto bad; |