1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sh.c,v 1.53 2006/10/31 11:07:05 debug Exp $ |
* $Id: cpu_sh.c,v 1.62 2007/03/08 19:04:09 debug Exp $ |
29 |
* |
* |
30 |
* Hitachi SuperH ("SH") CPU emulation. |
* Hitachi SuperH ("SH") CPU emulation. |
31 |
* |
* |
42 |
#include "cpu.h" |
#include "cpu.h" |
43 |
#include "device.h" |
#include "device.h" |
44 |
#include "float_emul.h" |
#include "float_emul.h" |
45 |
|
#include "interrupt.h" |
46 |
#include "machine.h" |
#include "machine.h" |
47 |
#include "memory.h" |
#include "memory.h" |
48 |
#include "misc.h" |
#include "misc.h" |
133 |
CPU_SETTINGS_ADD_REGISTER32("gbr", cpu->cd.sh.gbr); |
CPU_SETTINGS_ADD_REGISTER32("gbr", cpu->cd.sh.gbr); |
134 |
CPU_SETTINGS_ADD_REGISTER32("macl", cpu->cd.sh.macl); |
CPU_SETTINGS_ADD_REGISTER32("macl", cpu->cd.sh.macl); |
135 |
CPU_SETTINGS_ADD_REGISTER32("mach", cpu->cd.sh.mach); |
CPU_SETTINGS_ADD_REGISTER32("mach", cpu->cd.sh.mach); |
136 |
|
CPU_SETTINGS_ADD_REGISTER32("expevt", cpu->cd.sh.expevt); |
137 |
|
CPU_SETTINGS_ADD_REGISTER32("intevt", cpu->cd.sh.intevt); |
138 |
|
CPU_SETTINGS_ADD_REGISTER32("tra", cpu->cd.sh.tra); |
139 |
CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.sh.fpscr); |
CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.sh.fpscr); |
140 |
CPU_SETTINGS_ADD_REGISTER32("fpul", cpu->cd.sh.fpul); |
CPU_SETTINGS_ADD_REGISTER32("fpul", cpu->cd.sh.fpul); |
141 |
for (i=0; i<SH_N_GPRS; i++) { |
for (i=0; i<SH_N_GPRS; i++) { |
170 |
CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.utlb_lo[i]); |
CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.sh.utlb_lo[i]); |
171 |
} |
} |
172 |
|
|
173 |
|
/* Register the CPU's interrupts: */ |
174 |
|
for (i=SH_INTEVT_NMI; i<0x1000; i+=0x20) { |
175 |
|
struct interrupt template; |
176 |
|
char name[100]; |
177 |
|
snprintf(name, sizeof(name), "%s.irq[0x%x]", cpu->path, i); |
178 |
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memset(&template, 0, sizeof(template)); |
179 |
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template.line = i; |
180 |
|
template.name = name; |
181 |
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template.extra = cpu; |
182 |
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template.interrupt_assert = sh_cpu_interrupt_assert; |
183 |
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template.interrupt_deassert = sh_cpu_interrupt_deassert; |
184 |
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interrupt_handler_register(&template); |
185 |
|
} |
186 |
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|
187 |
/* SH4-specific memory mapped registers, TLBs, caches, etc: */ |
/* SH4-specific memory mapped registers, TLBs, caches, etc: */ |
188 |
if (cpu->cd.sh.cpu_type.arch == 4) |
if (cpu->cd.sh.cpu_type.arch == 4) |
189 |
device_add(machine, "sh4"); |
device_add(machine, "sh4"); |
193 |
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|
194 |
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|
195 |
/* |
/* |
196 |
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* sh_cpu_interrupt_assert(): |
197 |
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*/ |
198 |
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void sh_cpu_interrupt_assert(struct interrupt *interrupt) |
199 |
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{ |
200 |
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struct cpu *cpu = interrupt->extra; |
201 |
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int irq_nr = interrupt->line; |
202 |
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int word_index, bit_index; |
203 |
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|
204 |
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/* |
205 |
|
* Note: This gives higher interrupt priority to lower number |
206 |
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* interrupts. Hopefully this is correct. |
207 |
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*/ |
208 |
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|
209 |
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if (cpu->cd.sh.int_to_assert == 0 || irq_nr < cpu->cd.sh.int_to_assert) |
210 |
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cpu->cd.sh.int_to_assert = irq_nr; |
211 |
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|
212 |
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/* |
213 |
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* TODO: Keep track of all pending interrupts at multiple levels... |
214 |
|
* |
215 |
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* This is just a quick hack: |
216 |
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*/ |
217 |
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cpu->cd.sh.int_level = 1; |
218 |
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if (irq_nr == SH_INTEVT_TMU0_TUNI0) |
219 |
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 12) & 0xf; |
220 |
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if (irq_nr == SH_INTEVT_TMU1_TUNI1) |
221 |
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 8) & 0xf; |
222 |
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if (irq_nr == SH_INTEVT_TMU2_TUNI2) |
223 |
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 4) & 0xf; |
224 |
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if (irq_nr >= SH4_INTEVT_SCIF_ERI && |
225 |
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irq_nr <= SH4_INTEVT_SCIF_TXI) |
226 |
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_iprc >> 4) & 0xf; |
227 |
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|
228 |
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irq_nr /= 0x20; |
229 |
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word_index = irq_nr / (sizeof(uint32_t)*8); |
230 |
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bit_index = irq_nr & ((sizeof(uint32_t)*8) - 1); |
231 |
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|
232 |
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cpu->cd.sh.int_pending[word_index] |= (1 << bit_index); |
233 |
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} |
234 |
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|
235 |
|
|
236 |
|
/* |
237 |
|
* sh_cpu_interrupt_deassert(): |
238 |
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*/ |
239 |
|
void sh_cpu_interrupt_deassert(struct interrupt *interrupt) |
240 |
|
{ |
241 |
|
struct cpu *cpu = interrupt->extra; |
242 |
|
int irq_nr = interrupt->line; |
243 |
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int word_index, bit_index; |
244 |
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|
245 |
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if (cpu->cd.sh.int_to_assert == irq_nr) { |
246 |
|
/* |
247 |
|
* Rescan all interrupts to see if any are still asserted. |
248 |
|
* |
249 |
|
* Note: The scan only has to go from irq_nr + 0x20 to the max |
250 |
|
* index, since any lower interrupt cannot be asserted |
251 |
|
* at this time. |
252 |
|
*/ |
253 |
|
int i, max = 0x1000; |
254 |
|
cpu->cd.sh.int_to_assert = 0; |
255 |
|
|
256 |
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for (i=irq_nr+0x20; i<max; i+=0x20) { |
257 |
|
int j = i / 0x20; |
258 |
|
int word_index = j / (sizeof(uint32_t)*8); |
259 |
|
int bit_index = j & ((sizeof(uint32_t)*8) - 1); |
260 |
|
|
261 |
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/* Skip entire word if no bits are set: */ |
262 |
|
if (bit_index == 0 && |
263 |
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cpu->cd.sh.int_pending[word_index] == 0) |
264 |
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i += (sizeof(uint32_t)*8 - 1) * 0x20; |
265 |
|
else if (cpu->cd.sh.int_pending[word_index] |
266 |
|
& (1 << bit_index)) { |
267 |
|
cpu->cd.sh.int_to_assert = i; |
268 |
|
|
269 |
|
|
270 |
|
/* Hack. TODO: Fix. */ |
271 |
|
cpu->cd.sh.int_level = 1; |
272 |
|
if (i == SH_INTEVT_TMU0_TUNI0) |
273 |
|
cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 12) & 0xf; |
274 |
|
if (i == SH_INTEVT_TMU1_TUNI1) |
275 |
|
cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 8) & 0xf; |
276 |
|
if (i == SH_INTEVT_TMU2_TUNI2) |
277 |
|
cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 4) & 0xf; |
278 |
|
if (i >= SH4_INTEVT_SCIF_ERI && |
279 |
|
i <= SH4_INTEVT_SCIF_TXI) |
280 |
|
cpu->cd.sh.int_level = (cpu->cd.sh.intc_iprc >> 4) & 0xf; |
281 |
|
|
282 |
|
|
283 |
|
break; |
284 |
|
} |
285 |
|
} |
286 |
|
} |
287 |
|
|
288 |
|
irq_nr /= 0x20; |
289 |
|
word_index = irq_nr / (sizeof(uint32_t)*8); |
290 |
|
bit_index = irq_nr & ((sizeof(uint32_t)*8) - 1); |
291 |
|
|
292 |
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cpu->cd.sh.int_pending[word_index] &= ~(1 << bit_index); |
293 |
|
} |
294 |
|
|
295 |
|
|
296 |
|
/* |
297 |
* sh_cpu_list_available_types(): |
* sh_cpu_list_available_types(): |
298 |
* |
* |
299 |
* Print a list of available SH CPU types. |
* Print a list of available SH CPU types. |
521 |
|
|
522 |
|
|
523 |
/* |
/* |
|
* sh_cpu_interrupt(): |
|
|
* |
|
|
* Note: This gives higher interrupt priority to lower number interrupts. |
|
|
* Hopefully this is correct. |
|
|
*/ |
|
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int sh_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
|
|
{ |
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int word_index, bit_index; |
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|
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if (cpu->cd.sh.int_to_assert == 0 || irq_nr < cpu->cd.sh.int_to_assert) |
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cpu->cd.sh.int_to_assert = irq_nr; |
|
|
|
|
|
/* |
|
|
* TODO: Keep track of all pending interrupts at multiple levels... |
|
|
* |
|
|
* This is just a quick hack: |
|
|
*/ |
|
|
cpu->cd.sh.int_level = 1; |
|
|
if (irq_nr == SH_INTEVT_TMU0_TUNI0) |
|
|
cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 12) & 0xf; |
|
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if (irq_nr == SH_INTEVT_TMU1_TUNI1) |
|
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 8) & 0xf; |
|
|
if (irq_nr == SH_INTEVT_TMU2_TUNI2) |
|
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_ipra >> 4) & 0xf; |
|
|
if (irq_nr >= SH4_INTEVT_SCIF_ERI && |
|
|
irq_nr <= SH4_INTEVT_SCIF_TXI) |
|
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cpu->cd.sh.int_level = (cpu->cd.sh.intc_iprc >> 4) & 0xf; |
|
|
|
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irq_nr /= 0x20; |
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word_index = irq_nr / (sizeof(uint32_t)*8); |
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bit_index = irq_nr & ((sizeof(uint32_t)*8) - 1); |
|
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|
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cpu->cd.sh.int_pending[word_index] |= (1 << bit_index); |
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|
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return 0; |
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} |
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|
|
|
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/* |
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* sh_cpu_interrupt_ack(): |
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*/ |
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int sh_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
|
|
{ |
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int word_index, bit_index; |
|
|
|
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if (cpu->cd.sh.int_to_assert == irq_nr) { |
|
|
/* |
|
|
* Rescan all interrupts to see if any are still asserted. |
|
|
* |
|
|
* Note: The scan only has to go from irq_nr + 0x20 to the max |
|
|
* index, since any lower interrupt cannot be asserted |
|
|
* at this time. |
|
|
*/ |
|
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int i, max = 0x1000; |
|
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cpu->cd.sh.int_to_assert = 0; |
|
|
|
|
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for (i=irq_nr+0x20; i<max; i+=0x20) { |
|
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int j = i / 0x20; |
|
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int word_index = j / (sizeof(uint32_t)*8); |
|
|
int bit_index = j & ((sizeof(uint32_t)*8) - 1); |
|
|
|
|
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/* Skip entire word if no bits are set: */ |
|
|
if (bit_index == 0 && |
|
|
cpu->cd.sh.int_pending[word_index] == 0) |
|
|
i += (sizeof(uint32_t)*8 - 1) * 0x20; |
|
|
else if (cpu->cd.sh.int_pending[word_index] |
|
|
& (1 << bit_index)) { |
|
|
cpu->cd.sh.int_to_assert = i; |
|
|
break; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
irq_nr /= 0x20; |
|
|
word_index = irq_nr / (sizeof(uint32_t)*8); |
|
|
bit_index = irq_nr & ((sizeof(uint32_t)*8) - 1); |
|
|
|
|
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cpu->cd.sh.int_pending[word_index] &= ~(1 << bit_index); |
|
|
|
|
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return 0; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
524 |
* sh_update_sr(): |
* sh_update_sr(): |
525 |
* |
* |
526 |
* Writes a new value to the status register. |
* Writes a new value to the status register. |
659 |
cpu->cd.sh.spc += sizeof(uint16_t); |
cpu->cd.sh.spc += sizeof(uint16_t); |
660 |
break; |
break; |
661 |
|
|
662 |
|
case EXPEVT_RES_INST: |
663 |
|
/* |
664 |
|
* Note: Having this code here makes it possible to catch |
665 |
|
* reserved instructions; during normal instruction execution, |
666 |
|
* these are not very common. |
667 |
|
*/ |
668 |
|
#if 1 |
669 |
|
printf("\nRESERVED SuperH instruction at spc=%08"PRIx32"\n", |
670 |
|
cpu->cd.sh.spc); |
671 |
|
exit(1); |
672 |
|
#else |
673 |
|
break; |
674 |
|
#endif |
675 |
|
|
676 |
|
case EXPEVT_FPU_DISABLE: |
677 |
|
break; |
678 |
|
|
679 |
default:fatal("sh_exception(): exception 0x%x is not yet " |
default:fatal("sh_exception(): exception 0x%x is not yet " |
680 |
"implemented.\n", expevt); |
"implemented.\n", expevt); |
681 |
exit(1); |
exit(1); |
718 |
debug("stc\tsr,r%i\n", r8); |
debug("stc\tsr,r%i\n", r8); |
719 |
else if (lo8 == 0x03) |
else if (lo8 == 0x03) |
720 |
debug("bsrf\tr%i\n", r8); |
debug("bsrf\tr%i\n", r8); |
721 |
else if (lo4 == 0x4) |
else if (lo4 >= 4 && lo4 <= 6) { |
722 |
debug("mov.b\tr%i,@(r0,r%i)\n", r4, r8); |
if (lo4 == 0x4) |
723 |
else if (lo4 == 0x5) |
debug("mov.b\tr%i,@(r0,r%i)", r4, r8); |
724 |
debug("mov.w\tr%i,@(r0,r%i)\n", r4, r8); |
else if (lo4 == 0x5) |
725 |
else if (lo4 == 0x6) |
debug("mov.w\tr%i,@(r0,r%i)", r4, r8); |
726 |
debug("mov.l\tr%i,@(r0,r%i)\n", r4, r8); |
else if (lo4 == 0x6) |
727 |
else if (lo4 == 0x7) |
debug("mov.l\tr%i,@(r0,r%i)", r4, r8); |
728 |
|
if (running) { |
729 |
|
debug("\t; r0+r%i = 0x%08"PRIx32, r8, |
730 |
|
cpu->cd.sh.r[0] + cpu->cd.sh.r[r8]); |
731 |
|
} |
732 |
|
debug("\n"); |
733 |
|
} else if (lo4 == 0x7) |
734 |
debug("mul.l\tr%i,r%i\n", r4, r8); |
debug("mul.l\tr%i,r%i\n", r4, r8); |
735 |
else if (iword == 0x0008) |
else if (iword == 0x0008) |
736 |
debug("clrt\n"); |
debug("clrt\n"); |
740 |
debug("sts\tmach,r%i\n", r8); |
debug("sts\tmach,r%i\n", r8); |
741 |
else if (iword == 0x000b) |
else if (iword == 0x000b) |
742 |
debug("rts\n"); |
debug("rts\n"); |
743 |
else if (lo4 == 0xc) |
else if (lo4 >= 0xc && lo4 <= 0xe) { |
744 |
debug("mov.b\t@(r0,r%i),r%i\n", r4, r8); |
if (lo4 == 0xc) |
745 |
else if (lo4 == 0xd) |
debug("mov.b\t@(r0,r%i),r%i", r4, r8); |
746 |
debug("mov.w\t@(r0,r%i),r%i\n", r4, r8); |
else if (lo4 == 0xd) |
747 |
else if (lo4 == 0xe) |
debug("mov.w\t@(r0,r%i),r%i", r4, r8); |
748 |
debug("mov.l\t@(r0,r%i),r%i\n", r4, r8); |
else if (lo4 == 0xe) |
749 |
else if (lo8 == 0x12) |
debug("mov.l\t@(r0,r%i),r%i", r4, r8); |
750 |
|
if (running) { |
751 |
|
debug("\t; r0+r%i = 0x%08"PRIx32, r4, |
752 |
|
cpu->cd.sh.r[0] + cpu->cd.sh.r[r4]); |
753 |
|
} |
754 |
|
debug("\n"); |
755 |
|
} else if (lo8 == 0x12) |
756 |
debug("stc\tgbr,r%i\n", r8); |
debug("stc\tgbr,r%i\n", r8); |
757 |
else if (iword == 0x0018) |
else if (iword == 0x0018) |
758 |
debug("sett\n"); |
debug("sett\n"); |
804 |
debug("movca.l\tr0,@r%i\n", r8); |
debug("movca.l\tr0,@r%i\n", r8); |
805 |
else if (lo8 == 0xfa) |
else if (lo8 == 0xfa) |
806 |
debug("stc\tdbr,r%i\n", r8); |
debug("stc\tdbr,r%i\n", r8); |
807 |
else if (iword == 0x00ff) |
else if (iword == SH_INVALID_INSTR) |
808 |
debug("gxemul_dreamcast_prom_emul\n"); |
debug("gxemul_dreamcast_prom_emul\n"); |
809 |
else |
else |
810 |
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
811 |
break; |
break; |
812 |
case 0x1: |
case 0x1: |
813 |
debug("mov.l\tr%i,@(%i,r%i)\n", r4, lo4 * 4, r8); |
debug("mov.l\tr%i,@(%i,r%i)", r4, lo4 * 4, r8); |
814 |
|
if (running) { |
815 |
|
debug("\t; r%i+%i = 0x%08"PRIx32, r8, lo4 * 4, |
816 |
|
cpu->cd.sh.r[r8] + lo4 * 4); |
817 |
|
} |
818 |
|
debug("\n"); |
819 |
break; |
break; |
820 |
case 0x2: |
case 0x2: |
821 |
if (lo4 == 0x0) |
if (lo4 == 0x0) |
1000 |
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
1001 |
break; |
break; |
1002 |
case 0x5: |
case 0x5: |
1003 |
debug("mov.l\t@(%i,r%i),r%i\n", lo4 * 4, r4, r8); |
debug("mov.l\t@(%i,r%i),r%i", lo4 * 4, r4, r8); |
1004 |
|
if (running) { |
1005 |
|
debug("\t; r%i+%i = 0x%08"PRIx32, r4, lo4 * 4, |
1006 |
|
cpu->cd.sh.r[r4] + lo4 * 4); |
1007 |
|
} |
1008 |
|
debug("\n"); |
1009 |
break; |
break; |
1010 |
case 0x6: |
case 0x6: |
1011 |
if (lo4 == 0x0) |
if (lo4 == 0x0) |
1047 |
debug("add\t#%i,r%i\n", (int8_t)lo8, r8); |
debug("add\t#%i,r%i\n", (int8_t)lo8, r8); |
1048 |
break; |
break; |
1049 |
case 0x8: |
case 0x8: |
1050 |
if (r8 == 0x0) { |
if (r8 == 0 || r8 == 4) { |
1051 |
debug("mov.b\tr0,@(%i,r%i)\n", lo4, r4); |
if (r8 == 0x0) |
1052 |
} else if (r8 == 0x1) { |
debug("mov.b\tr0,@(%i,r%i)", lo4, r4); |
1053 |
debug("mov.w\tr0,@(%i,r%i)\n", lo4 * 2, r4); |
else if (r8 == 0x4) |
1054 |
} else if (r8 == 0x4) { |
debug("mov.b\t@(%i,r%i),r0", lo4, r4); |
1055 |
debug("mov.b\t@(%i,r%i),r0\n", lo4, r4); |
if (running) { |
1056 |
} else if (r8 == 0x5) { |
debug("\t; r%i+%i = 0x%08"PRIx32, r4, lo4, |
1057 |
debug("mov.w\t@(%i,r%i),r0\n", lo4 * 2, r4); |
cpu->cd.sh.r[r4] + lo4); |
1058 |
|
} |
1059 |
|
debug("\n"); |
1060 |
|
} else if (r8 == 1 || r8 == 5) { |
1061 |
|
if (r8 == 0x1) |
1062 |
|
debug("mov.w\tr0,@(%i,r%i)", lo4 * 2, r4); |
1063 |
|
else if (r8 == 0x5) |
1064 |
|
debug("mov.w\t@(%i,r%i),r0", lo4 * 2, r4); |
1065 |
|
if (running) { |
1066 |
|
debug("\t; r%i+%i = 0x%08"PRIx32, r4, lo4 * 2, |
1067 |
|
cpu->cd.sh.r[r4] + lo4 * 2); |
1068 |
|
} |
1069 |
|
debug("\n"); |
1070 |
} else if (r8 == 0x8) { |
} else if (r8 == 0x8) { |
1071 |
debug("cmp/eq\t#%i,r0\n", (int8_t)lo8); |
debug("cmp/eq\t#%i,r0\n", (int8_t)lo8); |
1072 |
} else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) { |
} else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) { |