1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc.c,v 1.12 2005/09/24 23:44:18 debug Exp $ |
* $Id: cpu_ppc.c,v 1.59 2006/06/24 21:47:23 debug Exp $ |
29 |
* |
* |
30 |
* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
40 |
#include "machine.h" |
#include "machine.h" |
41 |
#include "memory.h" |
#include "memory.h" |
42 |
#include "misc.h" |
#include "misc.h" |
43 |
|
#include "of.h" |
44 |
#include "opcodes_ppc.h" |
#include "opcodes_ppc.h" |
45 |
|
#include "ppc_bat.h" |
46 |
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#include "ppc_pte.h" |
47 |
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#include "ppc_spr.h" |
48 |
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#include "ppc_spr_strings.h" |
49 |
#include "symbol.h" |
#include "symbol.h" |
50 |
|
|
51 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
52 |
#include "tmp_ppc_head.c" |
#include "tmp_ppc_head.c" |
53 |
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54 |
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55 |
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void ppc_pc_to_pointers(struct cpu *); |
56 |
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void ppc32_pc_to_pointers(struct cpu *); |
57 |
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58 |
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|
59 |
/* |
/* |
60 |
* ppc_cpu_new(): |
* ppc_cpu_new(): |
61 |
* |
* |
93 |
|
|
94 |
/* Current operating mode: */ |
/* Current operating mode: */ |
95 |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
96 |
cpu->cd.ppc.pvr = cpu->cd.ppc.cpu_type.pvr; |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
97 |
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|
98 |
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/* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | |
99 |
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PPC_MSR_SF | PPC_MSR_FP; */ |
100 |
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|
101 |
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cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
102 |
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cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
103 |
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cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
104 |
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cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW; |
105 |
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cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs; |
106 |
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cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW; |
107 |
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cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs; |
108 |
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cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW; |
109 |
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cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs; |
110 |
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cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW; |
111 |
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cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs; |
112 |
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cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW; |
113 |
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cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs; |
114 |
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cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW; |
115 |
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|
116 |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
117 |
|
|
118 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
119 |
cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
120 |
cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
121 |
ppc32_invalidate_translation_caches_paddr; |
ppc32_invalidate_translation_caches; |
122 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
123 |
ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
124 |
} else { |
} else { |
125 |
cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
126 |
cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
127 |
ppc_invalidate_translation_caches_paddr; |
ppc_invalidate_translation_caches; |
128 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
129 |
ppc_invalidate_code_translation; |
ppc_invalidate_code_translation; |
130 |
} |
} |
131 |
|
|
132 |
cpu->translate_address = ppc_translate_address; |
cpu->translate_v2p = ppc_translate_v2p; |
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|
134 |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
135 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
155 |
} |
} |
156 |
} |
} |
157 |
|
|
158 |
cpu->cd.ppc.pir = cpu_id; |
cpu->cd.ppc.spr[SPR_PIR] = cpu_id; |
159 |
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|
160 |
/* Some default stack pointer value. TODO: move this? */ |
/* Some default stack pointer value. TODO: move this? */ |
161 |
cpu->cd.ppc.gpr[1] = machine->physical_ram_in_mb * 1048576 - 4096; |
cpu->cd.ppc.gpr[1] = machine->physical_ram_in_mb * 1048576 - 4096; |
230 |
/* |
/* |
231 |
* reg_access_msr(): |
* reg_access_msr(): |
232 |
*/ |
*/ |
233 |
void reg_access_msr(struct cpu *cpu, uint64_t *valuep, int writeflag) |
void reg_access_msr(struct cpu *cpu, uint64_t *valuep, int writeflag, |
234 |
|
int check_for_interrupts) |
235 |
{ |
{ |
236 |
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uint64_t old = cpu->cd.ppc.msr; |
237 |
|
|
238 |
if (valuep == NULL) { |
if (valuep == NULL) { |
239 |
fatal("reg_access_msr(): NULL\n"); |
fatal("reg_access_msr(): NULL\n"); |
240 |
return; |
return; |
241 |
} |
} |
242 |
|
|
243 |
if (writeflag) |
if (writeflag) { |
244 |
cpu->cd.ppc.msr = *valuep; |
cpu->cd.ppc.msr = *valuep; |
245 |
|
|
246 |
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/* Switching between temporary and real gpr 0..3? */ |
247 |
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if ((old & PPC_MSR_TGPR) != (cpu->cd.ppc.msr & PPC_MSR_TGPR)) { |
248 |
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int i; |
249 |
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for (i=0; i<PPC_N_TGPRS; i++) { |
250 |
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uint64_t t = cpu->cd.ppc.gpr[i]; |
251 |
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cpu->cd.ppc.gpr[i] = cpu->cd.ppc.tgpr[i]; |
252 |
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cpu->cd.ppc.tgpr[i] = t; |
253 |
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} |
254 |
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} |
255 |
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|
256 |
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if (cpu->cd.ppc.msr & PPC_MSR_IP) { |
257 |
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fatal("\n[ Reboot hack for NetBSD/prep. TODO: " |
258 |
|
"fix this. ]\n"); |
259 |
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cpu->running = 0; |
260 |
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} |
261 |
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} |
262 |
|
|
263 |
/* TODO: Is the little-endian bit writable? */ |
/* TODO: Is the little-endian bit writable? */ |
264 |
|
|
265 |
cpu->cd.ppc.msr &= ~PPC_MSR_LE; |
cpu->cd.ppc.msr &= ~PPC_MSR_LE; |
268 |
|
|
269 |
if (!writeflag) |
if (!writeflag) |
270 |
*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
271 |
|
|
272 |
|
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
273 |
|
if (cpu->cd.ppc.dec_intr_pending) { |
274 |
|
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
275 |
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cpu->cd.ppc.dec_intr_pending = 0; |
276 |
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} else if (cpu->cd.ppc.irq_asserted) |
277 |
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ppc_exception(cpu, PPC_EXCEPTION_EI); |
278 |
|
} |
279 |
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} |
280 |
|
|
281 |
|
|
282 |
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/* |
283 |
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* ppc_exception(): |
284 |
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*/ |
285 |
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void ppc_exception(struct cpu *cpu, int exception_nr) |
286 |
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{ |
287 |
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/* Save PC and MSR: */ |
288 |
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cpu->cd.ppc.spr[SPR_SRR0] = cpu->pc; |
289 |
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|
290 |
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if (exception_nr >= 0x10 && exception_nr <= 0x13) |
291 |
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cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0xffff) |
292 |
|
| (cpu->cd.ppc.cr & 0xf0000000); |
293 |
|
else |
294 |
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cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
295 |
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|
296 |
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if (!quiet_mode) |
297 |
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fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr, |
298 |
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(long long)cpu->pc); |
299 |
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|
300 |
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/* Disable External Interrupts, Recoverable Interrupt Mode, |
301 |
|
and go to Supervisor mode */ |
302 |
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cpu->cd.ppc.msr &= ~(PPC_MSR_EE | PPC_MSR_RI | PPC_MSR_PR); |
303 |
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|
304 |
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cpu->pc = exception_nr * 0x100; |
305 |
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if (cpu->cd.ppc.msr & PPC_MSR_IP) |
306 |
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cpu->pc += 0xfff00000ULL; |
307 |
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|
308 |
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if (cpu->is_32bit) |
309 |
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ppc32_pc_to_pointers(cpu); |
310 |
|
else |
311 |
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ppc_pc_to_pointers(cpu); |
312 |
} |
} |
313 |
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|
314 |
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|
334 |
|
|
335 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
336 |
if (bits32) |
if (bits32) |
337 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t)cpu->pc); |
338 |
else |
else |
339 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t)cpu->pc); |
340 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
341 |
|
|
342 |
debug("cpu%i: lr = 0x", x); |
debug("cpu%i: lr = 0x", x); |
343 |
if (bits32) |
if (bits32) |
344 |
debug("%08x", (int)cpu->cd.ppc.lr); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); |
345 |
else |
else |
346 |
debug("%016llx", (long long)cpu->cd.ppc.lr); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); |
347 |
debug(" cr = 0x%08x\n", (int)cpu->cd.ppc.cr); |
debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); |
348 |
|
|
|
debug("cpu%i: ctr = 0x", x); |
|
349 |
if (bits32) |
if (bits32) |
350 |
debug("%08x", (int)cpu->cd.ppc.ctr); |
debug(" "); |
351 |
|
else |
352 |
|
debug("\ncpu%i: ", x); |
353 |
|
debug("ctr = 0x", x); |
354 |
|
if (bits32) |
355 |
|
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); |
356 |
else |
else |
357 |
debug("%016llx", (long long)cpu->cd.ppc.ctr); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); |
358 |
|
|
359 |
debug(" xer = 0x", x); |
debug(" xer = 0x", x); |
360 |
if (bits32) |
if (bits32) |
361 |
debug("%08x\n", (int)cpu->cd.ppc.xer); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); |
362 |
else |
else |
363 |
debug("%016llx\n", (long long)cpu->cd.ppc.xer); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); |
364 |
|
|
365 |
|
debug("\n"); |
366 |
|
|
367 |
if (bits32) { |
if (bits32) { |
368 |
/* 32-bit: */ |
/* 32-bit: */ |
388 |
} |
} |
389 |
|
|
390 |
/* Other special registers: */ |
/* Other special registers: */ |
391 |
debug("cpu%i: srr0 = 0x%016llx srr1 = 0x%016llx\n", x, |
if (bits32) { |
392 |
(long long)cpu->cd.ppc.srr0, (long long)cpu->cd.ppc.srr1); |
debug("cpu%i: srr0 = 0x%08x srr1 = 0x%08x\n", x, |
393 |
reg_access_msr(cpu, &tmp, 0); |
(int)cpu->cd.ppc.spr[SPR_SRR0], |
394 |
debug("cpu%i: msr = 0x%016llx ", x, (long long)tmp); |
(int)cpu->cd.ppc.spr[SPR_SRR1]); |
395 |
debug("tb = 0x%08x%08x\n", |
} else { |
396 |
(int)cpu->cd.ppc.tbu, (int)cpu->cd.ppc.tbl); |
debug("cpu%i: srr0 = 0x%016llx srr1 = 0x%016llx\n", x, |
397 |
debug("cpu%i: dec = 0x%08x hdec = 0x%08x\n", |
(long long)cpu->cd.ppc.spr[SPR_SRR0], |
398 |
x, (int)cpu->cd.ppc.dec, (int)cpu->cd.ppc.hdec); |
(long long)cpu->cd.ppc.spr[SPR_SRR1]); |
399 |
|
} |
400 |
|
debug("cpu%i: msr = ", x); |
401 |
|
reg_access_msr(cpu, &tmp, 0, 0); |
402 |
|
if (bits32) |
403 |
|
debug("0x%08x ", (int)tmp); |
404 |
|
else |
405 |
|
debug("0x%016llx ", (long long)tmp); |
406 |
|
debug("tb = 0x%08x%08x\n", (int)cpu->cd.ppc.spr[SPR_TBU], |
407 |
|
(int)cpu->cd.ppc.spr[SPR_TBL]); |
408 |
|
debug("cpu%i: dec = 0x%08x", x, (int)cpu->cd.ppc.spr[SPR_DEC]); |
409 |
|
if (!bits32) |
410 |
|
debug(" hdec = 0x%08x\n", |
411 |
|
(int)cpu->cd.ppc.spr[SPR_HDEC]); |
412 |
|
debug("\n"); |
413 |
} |
} |
414 |
|
|
415 |
if (coprocs & 1) { |
if (coprocs & 1) { |
431 |
|
|
432 |
if (coprocs & 2) { |
if (coprocs & 2) { |
433 |
debug("cpu%i: sdr1 = 0x%llx\n", x, |
debug("cpu%i: sdr1 = 0x%llx\n", x, |
434 |
(long long)cpu->cd.ppc.sdr1); |
(long long)cpu->cd.ppc.spr[SPR_SDR1]); |
435 |
for (i=0; i<4; i++) |
if (cpu->cd.ppc.cpu_type.flags & PPC_601) |
436 |
debug("cpu%i: ibat%iu = 0x%08x ibat%il = 0x%08x\n", |
debug("cpu%i: PPC601-style, TODO!\n"); |
437 |
x, i, cpu->cd.ppc.ibat_u[i], |
else { |
438 |
i, cpu->cd.ppc.ibat_l[i]); |
for (i=0; i<8; i++) { |
439 |
for (i=0; i<4; i++) |
int spr = SPR_IBAT0U + i*2; |
440 |
debug("cpu%i: dbat%iu = 0x%08x dbat%il = 0x%08x\n", |
uint32_t upper = cpu->cd.ppc.spr[spr]; |
441 |
x, i, cpu->cd.ppc.dbat_u[i], |
uint32_t lower = cpu->cd.ppc.spr[spr+1]; |
442 |
i, cpu->cd.ppc.dbat_l[i]); |
uint32_t len = (((upper & BAT_BL) << 15) |
443 |
|
| 0x1ffff) + 1; |
444 |
|
debug("cpu%i: %sbat%i: u=0x%08x l=0x%08x ", |
445 |
|
x, i<4? "i" : "d", i&3, upper, lower); |
446 |
|
if (!(upper & BAT_V)) { |
447 |
|
debug(" (not valid)\n"); |
448 |
|
continue; |
449 |
|
} |
450 |
|
if (len < 1048576) |
451 |
|
debug(" (%i KB, ", len >> 10); |
452 |
|
else |
453 |
|
debug(" (%i MB, ", len >> 20); |
454 |
|
if (upper & BAT_Vu) |
455 |
|
debug("user, "); |
456 |
|
if (upper & BAT_Vs) |
457 |
|
debug("supervisor, "); |
458 |
|
if (lower & (BAT_W | BAT_I | BAT_M | BAT_G)) |
459 |
|
debug("%s%s%s%s, ", |
460 |
|
lower & BAT_W? "W" : "", |
461 |
|
lower & BAT_I? "I" : "", |
462 |
|
lower & BAT_M? "M" : "", |
463 |
|
lower & BAT_G? "G" : ""); |
464 |
|
switch (lower & BAT_PP) { |
465 |
|
case BAT_PP_NONE: debug("NO access"); break; |
466 |
|
case BAT_PP_RO_S: debug("read-only, soft"); |
467 |
|
break; |
468 |
|
case BAT_PP_RO: debug("read-only"); break; |
469 |
|
case BAT_PP_RW: debug("read/write"); break; |
470 |
|
} |
471 |
|
debug(")\n"); |
472 |
|
} |
473 |
|
} |
474 |
|
} |
475 |
|
|
476 |
|
if (coprocs & 4) { |
477 |
|
for (i=0; i<16; i++) { |
478 |
|
uint32_t s = cpu->cd.ppc.sr[i]; |
479 |
|
debug("cpu%i:", x); |
480 |
|
debug(" sr%2i = 0x%08x", i, (int)s); |
481 |
|
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
482 |
|
if (s != 0) { |
483 |
|
debug(" ("); |
484 |
|
if (s & SR_TYPE) { |
485 |
|
debug("NON-memory type"); |
486 |
|
s &= ~SR_TYPE; |
487 |
|
if (s != 0) |
488 |
|
debug(", "); |
489 |
|
} |
490 |
|
if (s & SR_SUKEY) { |
491 |
|
debug("supervisor-key"); |
492 |
|
s &= ~SR_SUKEY; |
493 |
|
if (s != 0) |
494 |
|
debug(", "); |
495 |
|
} |
496 |
|
if (s & SR_PRKEY) { |
497 |
|
debug("user-key"); |
498 |
|
s &= ~SR_PRKEY; |
499 |
|
if (s != 0) |
500 |
|
debug(", "); |
501 |
|
} |
502 |
|
if (s & SR_NOEXEC) |
503 |
|
debug("NOEXEC"); |
504 |
|
debug(")"); |
505 |
|
} |
506 |
|
debug("\n"); |
507 |
|
} |
508 |
} |
} |
509 |
} |
} |
510 |
|
|
536 |
*match_register = 1; |
*match_register = 1; |
537 |
} else if (strcasecmp(name, "lr") == 0) { |
} else if (strcasecmp(name, "lr") == 0) { |
538 |
if (writeflag) |
if (writeflag) |
539 |
m->cpus[cpunr]->cd.ppc.lr = *valuep; |
m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
540 |
else |
else |
541 |
*valuep = m->cpus[cpunr]->cd.ppc.lr; |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
542 |
*match_register = 1; |
*match_register = 1; |
543 |
} else if (strcasecmp(name, "cr") == 0) { |
} else if (strcasecmp(name, "cr") == 0) { |
544 |
if (writeflag) |
if (writeflag) |
548 |
*match_register = 1; |
*match_register = 1; |
549 |
} else if (strcasecmp(name, "dec") == 0) { |
} else if (strcasecmp(name, "dec") == 0) { |
550 |
if (writeflag) |
if (writeflag) |
551 |
m->cpus[cpunr]->cd.ppc.dec = *valuep; |
m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
552 |
else |
else |
553 |
*valuep = m->cpus[cpunr]->cd.ppc.dec; |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
554 |
*match_register = 1; |
*match_register = 1; |
555 |
} else if (strcasecmp(name, "hdec") == 0) { |
} else if (strcasecmp(name, "hdec") == 0) { |
556 |
if (writeflag) |
if (writeflag) |
557 |
m->cpus[cpunr]->cd.ppc.hdec = *valuep; |
m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
558 |
else |
else |
559 |
*valuep = m->cpus[cpunr]->cd.ppc.hdec; |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
560 |
*match_register = 1; |
*match_register = 1; |
561 |
} else if (strcasecmp(name, "ctr") == 0) { |
} else if (strcasecmp(name, "ctr") == 0) { |
562 |
if (writeflag) |
if (writeflag) |
563 |
m->cpus[cpunr]->cd.ppc.ctr = *valuep; |
m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
564 |
else |
else |
565 |
*valuep = m->cpus[cpunr]->cd.ppc.ctr; |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
566 |
*match_register = 1; |
*match_register = 1; |
567 |
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
568 |
int nr = atoi(name + 1); |
int nr = atoi(name + 1); |
575 |
} |
} |
576 |
} else if (strcasecmp(name, "xer") == 0) { |
} else if (strcasecmp(name, "xer") == 0) { |
577 |
if (writeflag) |
if (writeflag) |
578 |
m->cpus[cpunr]->cd.ppc.xer = *valuep; |
m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
579 |
else |
else |
580 |
*valuep = m->cpus[cpunr]->cd.ppc.xer; |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
581 |
*match_register = 1; |
*match_register = 1; |
582 |
} else if (strcasecmp(name, "fpscr") == 0) { |
} else if (strcasecmp(name, "fpscr") == 0) { |
583 |
if (writeflag) |
if (writeflag) |
599 |
|
|
600 |
|
|
601 |
/* |
/* |
602 |
* ppc_cpu_show_full_statistics(): |
* ppc_cpu_tlbdump(): |
603 |
* |
* |
604 |
* Show detailed statistics on opcode usage on each cpu. |
* Not currently used for PPC. |
605 |
*/ |
*/ |
606 |
void ppc_cpu_show_full_statistics(struct machine *m) |
void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
607 |
{ |
{ |
608 |
fatal("ppc_cpu_show_full_statistics(): TODO\n"); |
} |
609 |
|
|
610 |
|
|
611 |
|
static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
612 |
|
size_t maxlen, int len) |
613 |
|
{ |
614 |
|
char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
615 |
|
if (len == 4) |
616 |
|
value &= 0xffffffffULL; |
617 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
618 |
|
if (len == 4) { |
619 |
|
value = ((value & 0xff) << 24) + |
620 |
|
((value & 0xff00) << 8) + |
621 |
|
((value & 0xff0000) >> 8) + |
622 |
|
((value & 0xff000000) >> 24); |
623 |
|
} else { |
624 |
|
value = ((value & 0xff) << 56) + |
625 |
|
((value & 0xff00) << 40) + |
626 |
|
((value & 0xff0000) << 24) + |
627 |
|
((value & 0xff000000ULL) << 8) + |
628 |
|
((value & 0xff00000000ULL) >> 8) + |
629 |
|
((value & 0xff0000000000ULL) >> 24) + |
630 |
|
((value & 0xff000000000000ULL) >> 40) + |
631 |
|
((value & 0xff00000000000000ULL) >> 56); |
632 |
|
} |
633 |
|
} |
634 |
|
snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
635 |
} |
} |
636 |
|
|
637 |
|
|
638 |
/* |
/* |
639 |
* ppc_cpu_tlbdump(): |
* ppc_cpu_gdb_stub(): |
|
* |
|
|
* Called from the debugger to dump the TLB in a readable format. |
|
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
|
640 |
* |
* |
641 |
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
* Execute a "remote GDB" command. Returns a newly allocated response string |
642 |
* just dumped. |
* on success, NULL on failure. |
643 |
*/ |
*/ |
644 |
void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
char *ppc_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
645 |
{ |
{ |
646 |
fatal("ppc_cpu_tlbdump(): TODO\n"); |
if (strcmp(cmd, "g") == 0) { |
647 |
|
int i; |
648 |
|
char *r; |
649 |
|
size_t wlen = cpu->is_32bit? |
650 |
|
sizeof(uint32_t) : sizeof(uint64_t); |
651 |
|
size_t len = 1 + 76 * wlen; |
652 |
|
r = malloc(len); |
653 |
|
if (r == NULL) { |
654 |
|
fprintf(stderr, "out of memory\n"); |
655 |
|
exit(1); |
656 |
|
} |
657 |
|
r[0] = '\0'; |
658 |
|
for (i=0; i<128; i++) |
659 |
|
add_response_word(cpu, r, i, len, wlen); |
660 |
|
return r; |
661 |
|
} |
662 |
|
|
663 |
|
if (cmd[0] == 'p') { |
664 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
665 |
|
size_t wlen = cpu->is_32bit? |
666 |
|
sizeof(uint32_t) : sizeof(uint64_t); |
667 |
|
size_t len = 2 * wlen + 1; |
668 |
|
char *r = malloc(len); |
669 |
|
r[0] = '\0'; |
670 |
|
if (regnr >= 0 && regnr <= 31) { |
671 |
|
add_response_word(cpu, r, |
672 |
|
cpu->cd.ppc.gpr[regnr], len, wlen); |
673 |
|
} else if (regnr == 0x40) { |
674 |
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
675 |
|
} else if (regnr == 0x42) { |
676 |
|
add_response_word(cpu, r, cpu->cd.ppc.cr, len, wlen); |
677 |
|
} else if (regnr == 0x43) { |
678 |
|
add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_LR], |
679 |
|
len, wlen); |
680 |
|
} else if (regnr == 0x44) { |
681 |
|
add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_CTR], |
682 |
|
len, wlen); |
683 |
|
} else if (regnr == 0x45) { |
684 |
|
add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_XER], |
685 |
|
len, wlen); |
686 |
|
} else { |
687 |
|
/* Unimplemented: */ |
688 |
|
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
689 |
|
} |
690 |
|
return r; |
691 |
|
} |
692 |
|
|
693 |
|
fatal("ppc_cpu_gdb_stub(): TODO\n"); |
694 |
|
return NULL; |
695 |
} |
} |
696 |
|
|
697 |
|
|
698 |
/* |
/* |
699 |
* ppc_cpu_interrupt(): |
* ppc_cpu_interrupt(): |
700 |
|
* |
701 |
|
* 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, |
702 |
|
* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
703 |
|
* |
704 |
|
* TODO: don't hardcode to BeBox! |
705 |
*/ |
*/ |
706 |
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
707 |
{ |
{ |
708 |
fatal("ppc_cpu_interrupt(): TODO\n"); |
/* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
709 |
return 0; |
if (irq_nr <= 64) { |
710 |
|
if (cpu->machine->md_interrupt != NULL) |
711 |
|
cpu->machine->md_interrupt( |
712 |
|
cpu->machine, cpu, irq_nr, 1); |
713 |
|
else |
714 |
|
fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); |
715 |
|
} else { |
716 |
|
/* Assert PPC IRQ: */ |
717 |
|
cpu->cd.ppc.irq_asserted = 1; |
718 |
|
} |
719 |
|
return 1; |
720 |
} |
} |
721 |
|
|
722 |
|
|
725 |
*/ |
*/ |
726 |
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
727 |
{ |
{ |
728 |
/* fatal("ppc_cpu_interrupt_ack(): TODO\n"); */ |
if (irq_nr <= 64) { |
729 |
return 0; |
if (cpu->machine->md_interrupt != NULL) |
730 |
|
cpu->machine->md_interrupt(cpu->machine, |
731 |
|
cpu, irq_nr, 0); |
732 |
|
} else { |
733 |
|
/* De-assert PPC IRQ: */ |
734 |
|
cpu->cd.ppc.irq_asserted = 0; |
735 |
|
} |
736 |
|
return 1; |
737 |
} |
} |
738 |
|
|
739 |
|
|
750 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
751 |
*/ |
*/ |
752 |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
753 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
754 |
{ |
{ |
755 |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
756 |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
789 |
hi6 = iword >> 26; |
hi6 = iword >> 26; |
790 |
|
|
791 |
switch (hi6) { |
switch (hi6) { |
792 |
|
case 0x4: |
793 |
|
debug("ALTIVEC TODO"); |
794 |
|
/* vxor etc */ |
795 |
|
break; |
796 |
case PPC_HI6_MULLI: |
case PPC_HI6_MULLI: |
797 |
case PPC_HI6_SUBFIC: |
case PPC_HI6_SUBFIC: |
798 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
985 |
debug("unimplemented hi6_19, xo = 0x%x", xo); |
debug("unimplemented hi6_19, xo = 0x%x", xo); |
986 |
} |
} |
987 |
break; |
break; |
988 |
|
case PPC_HI6_RLWNM: |
989 |
case PPC_HI6_RLWIMI: |
case PPC_HI6_RLWIMI: |
990 |
case PPC_HI6_RLWINM: |
case PPC_HI6_RLWINM: |
991 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
992 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
993 |
sh = (iword >> 11) & 31; |
sh = (iword >> 11) & 31; /* actually rb for rlwnm */ |
994 |
mb = (iword >> 6) & 31; |
mb = (iword >> 6) & 31; |
995 |
me = (iword >> 1) & 31; |
me = (iword >> 1) & 31; |
996 |
rc = iword & 1; |
rc = iword & 1; |
997 |
switch (hi6) { |
switch (hi6) { |
998 |
|
case PPC_HI6_RLWNM: |
999 |
|
mnem = power? "rlnm" : "rlwnm"; break; |
1000 |
case PPC_HI6_RLWIMI: |
case PPC_HI6_RLWIMI: |
1001 |
mnem = power? "rlimi" : "rlwimi"; break; |
mnem = power? "rlimi" : "rlwimi"; break; |
1002 |
case PPC_HI6_RLWINM: |
case PPC_HI6_RLWINM: |
1003 |
mnem = power? "rlinm" : "rlwinm"; break; |
mnem = power? "rlinm" : "rlwinm"; break; |
1004 |
} |
} |
1005 |
debug("%s%s\tr%i,r%i,%i,%i,%i", |
debug("%s%s\tr%i,r%i,%s%i,%i,%i", |
1006 |
mnem, rc?".":"", ra, rs, sh, mb, me); |
mnem, rc?".":"", ra, rs, |
1007 |
|
hi6 == PPC_HI6_RLWNM? "r" : "", |
1008 |
|
sh, mb, me); |
1009 |
break; |
break; |
1010 |
case PPC_HI6_ORI: |
case PPC_HI6_ORI: |
1011 |
case PPC_HI6_ORIS: |
case PPC_HI6_ORIS: |
1044 |
case PPC_HI6_30: |
case PPC_HI6_30: |
1045 |
xo = (iword >> 2) & 7; |
xo = (iword >> 2) & 7; |
1046 |
switch (xo) { |
switch (xo) { |
1047 |
|
case PPC_30_RLDICL: |
1048 |
case PPC_30_RLDICR: |
case PPC_30_RLDICR: |
1049 |
|
case PPC_30_RLDIMI: /* mb, not me */ |
1050 |
|
mnem = NULL; |
1051 |
|
switch (xo) { |
1052 |
|
case PPC_30_RLDICL: mnem = "rldicl"; break; |
1053 |
|
case PPC_30_RLDICR: mnem = "rldicr"; break; |
1054 |
|
case PPC_30_RLDIMI: mnem = "rldimi"; break; |
1055 |
|
} |
1056 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
1057 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
1058 |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
1059 |
me = ((iword >> 6) & 31) | (iword & 0x20); |
me = ((iword >> 6) & 31) | (iword & 0x20); |
1060 |
rc = iword & 1; |
rc = iword & 1; |
1061 |
debug("rldicr%s\tr%i,r%i,%i,%i", |
debug("%s%s\tr%i,r%i,%i,%i", |
1062 |
rc?".":"", ra, rs, sh, me); |
mnem, rc?".":"", ra, rs, sh, me); |
1063 |
break; |
break; |
1064 |
default: |
default: |
1065 |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
1119 |
case PPC_31_LDARX: |
case PPC_31_LDARX: |
1120 |
case PPC_31_LBZX: |
case PPC_31_LBZX: |
1121 |
case PPC_31_LBZUX: |
case PPC_31_LBZUX: |
1122 |
|
case PPC_31_LHAX: |
1123 |
|
case PPC_31_LHAUX: |
1124 |
case PPC_31_LHZX: |
case PPC_31_LHZX: |
1125 |
case PPC_31_LHZUX: |
case PPC_31_LHZUX: |
1126 |
case PPC_31_LWZX: |
case PPC_31_LWZX: |
1127 |
case PPC_31_LWZUX: |
case PPC_31_LWZUX: |
1128 |
|
case PPC_31_LHBRX: |
1129 |
|
case PPC_31_LWBRX: |
1130 |
|
case PPC_31_LFDX: |
1131 |
|
case PPC_31_LFSX: |
1132 |
case PPC_31_STWCX_DOT: |
case PPC_31_STWCX_DOT: |
1133 |
case PPC_31_STDCX_DOT: |
case PPC_31_STDCX_DOT: |
1134 |
case PPC_31_STBX: |
case PPC_31_STBX: |
1139 |
case PPC_31_STWUX: |
case PPC_31_STWUX: |
1140 |
case PPC_31_STDX: |
case PPC_31_STDX: |
1141 |
case PPC_31_STDUX: |
case PPC_31_STDUX: |
1142 |
|
case PPC_31_STHBRX: |
1143 |
|
case PPC_31_STWBRX: |
1144 |
|
case PPC_31_STFDX: |
1145 |
|
case PPC_31_STFSX: |
1146 |
/* rs for stores, rt for loads, actually */ |
/* rs for stores, rt for loads, actually */ |
1147 |
load = 0; wlen = 0; |
load = 0; wlen = 0; fpreg = 0; |
1148 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
1149 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
1150 |
rb = (iword >> 11) & 31; |
rb = (iword >> 11) & 31; |
1153 |
case PPC_31_LDARX: wlen=8;load=1; mnem = "ldarx"; break; |
case PPC_31_LDARX: wlen=8;load=1; mnem = "ldarx"; break; |
1154 |
case PPC_31_LBZX: wlen=1;load=1; mnem = "lbzx"; break; |
case PPC_31_LBZX: wlen=1;load=1; mnem = "lbzx"; break; |
1155 |
case PPC_31_LBZUX: wlen=1;load=1; mnem = "lbzux"; break; |
case PPC_31_LBZUX: wlen=1;load=1; mnem = "lbzux"; break; |
1156 |
|
case PPC_31_LHAX: wlen=2;load=1; mnem = "lhax"; break; |
1157 |
|
case PPC_31_LHAUX: wlen=2;load=1; mnem = "lhaux"; break; |
1158 |
case PPC_31_LHZX: wlen=2;load=1; mnem = "lhzx"; break; |
case PPC_31_LHZX: wlen=2;load=1; mnem = "lhzx"; break; |
1159 |
case PPC_31_LHZUX: wlen=2;load=1; mnem = "lhzux"; break; |
case PPC_31_LHZUX: wlen=2;load=1; mnem = "lhzux"; break; |
1160 |
case PPC_31_LWZX: wlen = 4; load = 1; |
case PPC_31_LWZX: wlen = 4; load = 1; |
1163 |
case PPC_31_LWZUX: wlen = 4; load = 1; |
case PPC_31_LWZUX: wlen = 4; load = 1; |
1164 |
mnem = power? "lux":"lwzux"; |
mnem = power? "lux":"lwzux"; |
1165 |
break; |
break; |
1166 |
|
case PPC_31_LFDX: fpreg = 1; wlen = 8; load = 1; |
1167 |
|
mnem = "lfdx"; break; |
1168 |
|
case PPC_31_LFSX: fpreg = 1; wlen = 4; load = 1; |
1169 |
|
mnem = "lfsx"; break; |
1170 |
case PPC_31_STWCX_DOT: wlen=4; mnem = "stwcx."; break; |
case PPC_31_STWCX_DOT: wlen=4; mnem = "stwcx."; break; |
1171 |
case PPC_31_STDCX_DOT: wlen=8; mnem = "stdcx."; break; |
case PPC_31_STDCX_DOT: wlen=8; mnem = "stdcx."; break; |
1172 |
case PPC_31_STBX: wlen=1; mnem = "stbx"; break; |
case PPC_31_STBX: wlen=1; mnem = "stbx"; break; |
1181 |
break; |
break; |
1182 |
case PPC_31_STDX: wlen = 8; mnem = "stdx"; break; |
case PPC_31_STDX: wlen = 8; mnem = "stdx"; break; |
1183 |
case PPC_31_STDUX: wlen = 8; mnem = "stdux"; break; |
case PPC_31_STDUX: wlen = 8; mnem = "stdux"; break; |
1184 |
|
case PPC_31_LHBRX: wlen = 2; mnem = "lhbrx"; break; |
1185 |
|
case PPC_31_LWBRX: wlen = 4; mnem = power? |
1186 |
|
"lbrx" : "lwbrx"; break; |
1187 |
|
case PPC_31_STHBRX: wlen = 2; mnem = "sthbrx"; break; |
1188 |
|
case PPC_31_STWBRX: wlen = 4; mnem = power? |
1189 |
|
"stbrx" : "stwbrx"; break; |
1190 |
|
case PPC_31_STFDX: fpreg = 1; wlen = 8; |
1191 |
|
mnem = "stfdx"; break; |
1192 |
|
case PPC_31_STFSX: fpreg = 1; wlen = 4; |
1193 |
|
mnem = "stfsx"; break; |
1194 |
} |
} |
1195 |
debug("%s\tr%i,r%i,r%i", mnem, rs, ra, rb); |
debug("%s\t%s%i,r%i,r%i", mnem, |
1196 |
|
fpreg? "f" : "r", rs, ra, rb); |
1197 |
if (!running) |
if (!running) |
1198 |
break; |
break; |
1199 |
addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + |
addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + |
1200 |
cpu->cd.ppc.gpr[rb]; |
cpu->cd.ppc.gpr[rb]; |
1201 |
|
if (cpu->cd.ppc.bits == 32) |
1202 |
|
addr &= 0xffffffff; |
1203 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1204 |
addr, &offset); |
addr, &offset); |
1205 |
if (symbol != NULL) |
if (symbol != NULL) |
1206 |
debug(" \t<%s", symbol); |
debug(" \t<%s", symbol); |
1207 |
else |
else |
1208 |
debug(" \t<0x%llx", (long long)addr); |
debug(" \t<0x%llx", (long long)addr); |
1209 |
if (wlen > 0) { |
if (wlen > 0 && !fpreg /* && !reverse */) { |
1210 |
/* TODO */ |
/* TODO */ |
1211 |
} |
} |
1212 |
debug(">"); |
debug(">"); |
1223 |
} |
} |
1224 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra); |
1225 |
break; |
break; |
1226 |
|
case PPC_31_WRTEEI: |
1227 |
|
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
1228 |
|
break; |
1229 |
|
case PPC_31_MTMSRD: |
1230 |
|
/* TODO: Just a guess based on MTMSR */ |
1231 |
|
rs = (iword >> 21) & 31; |
1232 |
|
l_bit = (iword >> 16) & 1; |
1233 |
|
debug("mtmsrd\tr%i", rs); |
1234 |
|
if (l_bit) |
1235 |
|
debug(",%i", l_bit); |
1236 |
|
break; |
1237 |
case PPC_31_ADDZE: |
case PPC_31_ADDZE: |
1238 |
case PPC_31_ADDZEO: |
case PPC_31_ADDZEO: |
1239 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1251 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra); |
1252 |
break; |
break; |
1253 |
case PPC_31_MTSR: |
case PPC_31_MTSR: |
1254 |
/* Move to segment register */ |
case PPC_31_MFSR: |
1255 |
|
/* Move to/from segment register */ |
1256 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1257 |
ra = (iword >> 16) & 15; /* actually: sr */ |
ra = (iword >> 16) & 15; /* actually: sr */ |
1258 |
debug("mtsr\t%i,r%i", ra, rt); |
switch (xo) { |
1259 |
|
case PPC_31_MTSR: mnem = "mtsr"; break; |
1260 |
|
case PPC_31_MFSR: mnem = "mfsr"; break; |
1261 |
|
} |
1262 |
|
debug("%s\tr%i,%i", mnem, rt, ra); |
1263 |
break; |
break; |
1264 |
case PPC_31_MTSRIN: |
case PPC_31_MTSRIN: |
1265 |
case PPC_31_MFSRIN: |
case PPC_31_MFSRIN: |
1290 |
case PPC_31_SUBFCO: |
case PPC_31_SUBFCO: |
1291 |
case PPC_31_SUBFE: |
case PPC_31_SUBFE: |
1292 |
case PPC_31_SUBFEO: |
case PPC_31_SUBFEO: |
1293 |
|
case PPC_31_SUBFME: |
1294 |
|
case PPC_31_SUBFMEO: |
1295 |
case PPC_31_SUBFZE: |
case PPC_31_SUBFZE: |
1296 |
case PPC_31_SUBFZEO: |
case PPC_31_SUBFZEO: |
1297 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1337 |
case PPC_31_SUBF: mnem = "subf"; break; |
case PPC_31_SUBF: mnem = "subf"; break; |
1338 |
case PPC_31_SUBFO: mnem = "subfo"; break; |
case PPC_31_SUBFO: mnem = "subfo"; break; |
1339 |
case PPC_31_SUBFC: |
case PPC_31_SUBFC: |
1340 |
mnem = power? "sf" : "subfc"; |
mnem = power? "sf" : "subfc"; break; |
|
break; |
|
1341 |
case PPC_31_SUBFCO: |
case PPC_31_SUBFCO: |
1342 |
mnem = power? "sfo" : "subfco"; |
mnem = power? "sfo" : "subfco"; break; |
|
break; |
|
1343 |
case PPC_31_SUBFE: |
case PPC_31_SUBFE: |
1344 |
mnem = power? "sfe" : "subfe"; |
mnem = power? "sfe" : "subfe"; break; |
|
break; |
|
1345 |
case PPC_31_SUBFEO: |
case PPC_31_SUBFEO: |
1346 |
mnem = power? "sfeo" : "subfeo"; |
mnem = power? "sfeo" : "subfeo"; break; |
1347 |
break; |
case PPC_31_SUBFME: |
1348 |
|
mnem = power? "sfme" : "subfme"; break; |
1349 |
|
case PPC_31_SUBFMEO: |
1350 |
|
mnem = power? "sfmeo" : "subfmeo"; break; |
1351 |
case PPC_31_SUBFZE: |
case PPC_31_SUBFZE: |
1352 |
mnem = power? "sfze" : "subfze"; |
mnem = power? "sfze" : "subfze"; |
1353 |
no_rb = 1; |
no_rb = 1; |
1365 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1366 |
spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31); |
spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31); |
1367 |
switch (spr) { |
switch (spr) { |
1368 |
|
/* Some very common ones: */ |
1369 |
case 8: debug("mflr\tr%i", rt); break; |
case 8: debug("mflr\tr%i", rt); break; |
1370 |
case 9: debug("mfctr\tr%i", rt); break; |
case 9: debug("mfctr\tr%i", rt); break; |
|
case 26: debug("mfsrr0\tr%i", rt); break; |
|
|
case 27: debug("mfsrr1\tr%i", rt); break; |
|
|
case 272: debug("mfsprg\t0,r%i", rt); break; |
|
|
case 273: debug("mfsprg\t1,r%i", rt); break; |
|
|
case 274: debug("mfsprg\t2,r%i", rt); break; |
|
|
case 275: debug("mfsprg\t3,r%i", rt); break; |
|
|
case 287: debug("mfpvr\tr%i", rt); break; |
|
|
/* TODO: 1008 = hid0? */ |
|
|
case 1008: debug("mfdbsr\tr%i", rt); break; |
|
|
case 1009: debug("mfhid1\tr%i", rt); break; |
|
|
case 1017: debug("mfl2cr\tr%i", rt); break; |
|
|
case 1018: debug("mfl3cr\tr%i", rt); break; |
|
1371 |
default:debug("mfspr\tr%i,spr%i", rt, spr); |
default:debug("mfspr\tr%i,spr%i", rt, spr); |
1372 |
} |
} |
1373 |
|
if (spr == 8 || spr == 9) |
1374 |
|
debug("\t"); |
1375 |
|
debug("\t<%s%s", running? "read from " : "", |
1376 |
|
ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); |
1377 |
|
if (running) { |
1378 |
|
if (cpu->cd.ppc.bits == 32) |
1379 |
|
debug(": 0x%x", (int) |
1380 |
|
cpu->cd.ppc.spr[spr]); |
1381 |
|
else |
1382 |
|
debug(": 0x%llx", (long long) |
1383 |
|
cpu->cd.ppc.spr[spr]); |
1384 |
|
} |
1385 |
|
debug(">"); |
1386 |
|
break; |
1387 |
|
case PPC_31_TLBIA: |
1388 |
|
debug("tlbia"); |
1389 |
|
break; |
1390 |
|
case PPC_31_SLBIA: |
1391 |
|
debug("slbia"); |
1392 |
|
break; |
1393 |
|
case PPC_31_TLBLD: |
1394 |
|
case PPC_31_TLBLI: |
1395 |
|
rb = (iword >> 11) & 31; |
1396 |
|
debug("tlbl%s\tr%i", xo == PPC_31_TLBLD? "d" : "i", rb); |
1397 |
break; |
break; |
1398 |
case PPC_31_TLBIE: |
case PPC_31_TLBIE: |
1399 |
/* TODO: what is ra? The IBM online docs didn't say */ |
/* TODO: what is ra? The IBM online docs didn't say */ |
1404 |
else |
else |
1405 |
debug("tlbie\tr%i", rb); |
debug("tlbie\tr%i", rb); |
1406 |
break; |
break; |
1407 |
|
case PPC_31_TLBSX_DOT: |
1408 |
|
rs = (iword >> 21) & 31; |
1409 |
|
ra = (iword >> 16) & 31; |
1410 |
|
rb = (iword >> 11) & 31; |
1411 |
|
debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb); |
1412 |
|
break; |
1413 |
case PPC_31_TLBSYNC: |
case PPC_31_TLBSYNC: |
1414 |
debug("tlbsync"); |
debug("tlbsync"); |
1415 |
break; |
break; |
1454 |
debug("%s\tr%i,r%i", mnem, ra, rb); |
debug("%s\tr%i,r%i", mnem, ra, rb); |
1455 |
break; |
break; |
1456 |
case PPC_31_SLW: |
case PPC_31_SLW: |
1457 |
|
case PPC_31_SLD: |
1458 |
case PPC_31_SRAW: |
case PPC_31_SRAW: |
1459 |
case PPC_31_SRW: |
case PPC_31_SRW: |
1460 |
case PPC_31_AND: |
case PPC_31_AND: |
1461 |
case PPC_31_ANDC: |
case PPC_31_ANDC: |
1462 |
case PPC_31_NOR: |
case PPC_31_NOR: |
1463 |
|
case PPC_31_EQV: |
1464 |
case PPC_31_OR: |
case PPC_31_OR: |
1465 |
case PPC_31_ORC: |
case PPC_31_ORC: |
1466 |
case PPC_31_XOR: |
case PPC_31_XOR: |
1475 |
switch (xo) { |
switch (xo) { |
1476 |
case PPC_31_SLW: mnem = |
case PPC_31_SLW: mnem = |
1477 |
power? "sl" : "slw"; break; |
power? "sl" : "slw"; break; |
1478 |
|
case PPC_31_SLD: mnem = "sld"; break; |
1479 |
case PPC_31_SRAW: mnem = |
case PPC_31_SRAW: mnem = |
1480 |
power? "sra" : "sraw"; break; |
power? "sra" : "sraw"; break; |
1481 |
case PPC_31_SRW: mnem = |
case PPC_31_SRW: mnem = |
1484 |
case PPC_31_NAND: mnem = "nand"; break; |
case PPC_31_NAND: mnem = "nand"; break; |
1485 |
case PPC_31_ANDC: mnem = "andc"; break; |
case PPC_31_ANDC: mnem = "andc"; break; |
1486 |
case PPC_31_NOR: mnem = "nor"; break; |
case PPC_31_NOR: mnem = "nor"; break; |
1487 |
|
case PPC_31_EQV: mnem = "eqv"; break; |
1488 |
case PPC_31_OR: mnem = "or"; break; |
case PPC_31_OR: mnem = "or"; break; |
1489 |
case PPC_31_ORC: mnem = "orc"; break; |
case PPC_31_ORC: mnem = "orc"; break; |
1490 |
case PPC_31_XOR: mnem = "xor"; break; |
case PPC_31_XOR: mnem = "xor"; break; |
1525 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
1526 |
spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31); |
spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31); |
1527 |
switch (spr) { |
switch (spr) { |
1528 |
|
/* Some very common ones: */ |
1529 |
case 8: debug("mtlr\tr%i", rs); break; |
case 8: debug("mtlr\tr%i", rs); break; |
1530 |
case 9: debug("mtctr\tr%i", rs); break; |
case 9: debug("mtctr\tr%i", rs); break; |
|
case 26: debug("mtsrr0\tr%i", rs); break; |
|
|
case 27: debug("mtsrr1\tr%i", rs); break; |
|
|
case 272: debug("mtsprg\t0,r%i", rs); break; |
|
|
case 273: debug("mtsprg\t1,r%i", rs); break; |
|
|
case 274: debug("mtsprg\t2,r%i", rs); break; |
|
|
case 275: debug("mtsprg\t3,r%i", rs); break; |
|
|
case 528: debug("mtibatu\t0,r%i", rs); break; |
|
|
case 529: debug("mtibatl\t0,r%i", rs); break; |
|
|
case 530: debug("mtibatu\t1,r%i", rs); break; |
|
|
case 531: debug("mtibatl\t1,r%i", rs); break; |
|
|
case 532: debug("mtibatu\t2,r%i", rs); break; |
|
|
case 533: debug("mtibatl\t2,r%i", rs); break; |
|
|
case 534: debug("mtibatu\t3,r%i", rs); break; |
|
|
case 535: debug("mtibatl\t3,r%i", rs); break; |
|
|
case 536: debug("mtdbatu\t0,r%i", rs); break; |
|
|
case 537: debug("mtdbatl\t0,r%i", rs); break; |
|
|
case 538: debug("mtdbatu\t1,r%i", rs); break; |
|
|
case 539: debug("mtdbatl\t1,r%i", rs); break; |
|
|
case 540: debug("mtdbatu\t2,r%i", rs); break; |
|
|
case 541: debug("mtdbatl\t2,r%i", rs); break; |
|
|
case 542: debug("mtdbatu\t3,r%i", rs); break; |
|
|
case 543: debug("mtdbatl\t3,r%i", rs); break; |
|
|
case 1008: debug("mtdbsr\tr%i", rs); break; |
|
1531 |
default:debug("mtspr\tspr%i,r%i", spr, rs); |
default:debug("mtspr\tspr%i,r%i", spr, rs); |
1532 |
} |
} |
1533 |
|
if (spr == 8 || spr == 9) |
1534 |
|
debug("\t"); |
1535 |
|
debug("\t<%s%s", running? "write to " : "", |
1536 |
|
ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); |
1537 |
|
if (running) { |
1538 |
|
if (cpu->cd.ppc.bits == 32) |
1539 |
|
debug(": 0x%x", (int) |
1540 |
|
cpu->cd.ppc.gpr[rs]); |
1541 |
|
else |
1542 |
|
debug(": 0x%llx", (long long) |
1543 |
|
cpu->cd.ppc.gpr[rs]); |
1544 |
|
} |
1545 |
|
debug(">"); |
1546 |
break; |
break; |
1547 |
case PPC_31_SYNC: |
case PPC_31_SYNC: |
1548 |
debug("%s", power? "dcs" : "sync"); |
debug("%s", power? "dcs" : "sync"); |
1560 |
} |
} |
1561 |
debug("%s\tr%i,r%i,%i", mnem, rs, ra, nb); |
debug("%s\tr%i,r%i,%i", mnem, rs, ra, nb); |
1562 |
break; |
break; |
|
case PPC_31_LHBRX: |
|
|
case PPC_31_LWBRX: |
|
|
case PPC_31_STHBRX: |
|
|
case PPC_31_STWBRX: |
|
|
rt = (iword >> 21) & 31; /* stores use rs */ |
|
|
ra = (iword >> 16) & 31; |
|
|
rb = (iword >> 11) & 31; |
|
|
switch (xo) { |
|
|
case PPC_31_LHBRX: mnem = "lhbrx"; break; |
|
|
case PPC_31_LWBRX: mnem = power? |
|
|
"lbrx" : "lwbrx"; break; |
|
|
case PPC_31_STHBRX: mnem = "sthbrx"; break; |
|
|
case PPC_31_STWBRX: mnem = power? |
|
|
"stbrx" : "stwbrx"; break; |
|
|
} |
|
|
debug("%s\tr%i,r%i,r%i", mnem, rt, ra, rb); |
|
|
break; |
|
1563 |
case PPC_31_SRAWI: |
case PPC_31_SRAWI: |
1564 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
1565 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
1569 |
debug("%s%s\tr%i,r%i,%i", mnem, |
debug("%s%s\tr%i,r%i,%i", mnem, |
1570 |
rc? "." : "", ra, rs, sh); |
rc? "." : "", ra, rs, sh); |
1571 |
break; |
break; |
1572 |
|
case PPC_31_DSSALL: |
1573 |
|
debug("dssall"); |
1574 |
|
break; |
1575 |
case PPC_31_EIEIO: |
case PPC_31_EIEIO: |
1576 |
debug("%s", power? "eieio?" : "eieio"); |
debug("%s", power? "eieio?" : "eieio"); |
1577 |
break; |
break; |
1594 |
} |
} |
1595 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
1596 |
break; |
break; |
1597 |
|
case PPC_31_LVX: |
1598 |
|
case PPC_31_LVXL: |
1599 |
|
case PPC_31_STVX: |
1600 |
|
case PPC_31_STVXL: |
1601 |
|
rs = (iword >> 21) & 31; /* vs for stores, */ |
1602 |
|
ra = (iword >> 16) & 31; /* rs=vl for loads */ |
1603 |
|
rb = (iword >> 11) & 31; |
1604 |
|
rc = iword & 1; |
1605 |
|
switch (xo) { |
1606 |
|
case PPC_31_LVX: mnem = "lvx"; break; |
1607 |
|
case PPC_31_LVXL: mnem = "lvxl"; break; |
1608 |
|
case PPC_31_STVX: mnem = "stvx"; break; |
1609 |
|
case PPC_31_STVXL: mnem = "stvxl"; break; |
1610 |
|
} |
1611 |
|
debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", |
1612 |
|
rs, ra, rb); |
1613 |
|
break; |
1614 |
default: |
default: |
1615 |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
1616 |
} |
} |
1617 |
break; |
break; |
1618 |
|
case PPC_HI6_LD: |
1619 |
case PPC_HI6_LWZ: |
case PPC_HI6_LWZ: |
1620 |
case PPC_HI6_LWZU: |
case PPC_HI6_LWZU: |
1621 |
case PPC_HI6_LHZ: |
case PPC_HI6_LHZ: |
1624 |
case PPC_HI6_LHAU: |
case PPC_HI6_LHAU: |
1625 |
case PPC_HI6_LBZ: |
case PPC_HI6_LBZ: |
1626 |
case PPC_HI6_LBZU: |
case PPC_HI6_LBZU: |
1627 |
|
case PPC_HI6_LFD: |
1628 |
|
case PPC_HI6_LFS: |
1629 |
case PPC_HI6_LMW: |
case PPC_HI6_LMW: |
1630 |
|
case PPC_HI6_STD: |
1631 |
case PPC_HI6_STW: |
case PPC_HI6_STW: |
1632 |
case PPC_HI6_STWU: |
case PPC_HI6_STWU: |
1633 |
case PPC_HI6_STH: |
case PPC_HI6_STH: |
1635 |
case PPC_HI6_STB: |
case PPC_HI6_STB: |
1636 |
case PPC_HI6_STBU: |
case PPC_HI6_STBU: |
1637 |
case PPC_HI6_STMW: |
case PPC_HI6_STMW: |
|
case PPC_HI6_LFD: |
|
1638 |
case PPC_HI6_STFD: |
case PPC_HI6_STFD: |
1639 |
|
case PPC_HI6_STFS: |
1640 |
/* NOTE: Loads use rt, not rs, but are otherwise similar |
/* NOTE: Loads use rt, not rs, but are otherwise similar |
1641 |
to stores */ |
to stores */ |
1642 |
load = 0; wlen = 0; |
load = 0; wlen = 0; |
1645 |
imm = (int16_t)(iword & 0xffff); |
imm = (int16_t)(iword & 0xffff); |
1646 |
fpreg = 0; |
fpreg = 0; |
1647 |
switch (hi6) { |
switch (hi6) { |
1648 |
|
case PPC_HI6_LD: load=1; wlen = 8; mnem = "ld"; break; |
1649 |
case PPC_HI6_LWZ: load=1; wlen = 4; |
case PPC_HI6_LWZ: load=1; wlen = 4; |
1650 |
mnem = power? "l" : "lwz"; break; |
mnem = power? "l" : "lwz"; break; |
1651 |
case PPC_HI6_LWZU: load=1; wlen = 4; |
case PPC_HI6_LWZU: load=1; wlen = 4; |
1662 |
mnem = "lbz"; break; |
mnem = "lbz"; break; |
1663 |
case PPC_HI6_LBZU: load=1; wlen = 1; |
case PPC_HI6_LBZU: load=1; wlen = 1; |
1664 |
mnem = "lbzu"; break; |
mnem = "lbzu"; break; |
1665 |
|
case PPC_HI6_LFD: load=1; fpreg=1; wlen=8; mnem = "lfd"; break; |
1666 |
|
case PPC_HI6_LFS: load=1; fpreg=1; wlen=4; mnem = "lfs"; break; |
1667 |
|
case PPC_HI6_STD: wlen=8; mnem = "std"; break; |
1668 |
case PPC_HI6_STW: wlen=4; mnem = power? "st" : "stw"; break; |
case PPC_HI6_STW: wlen=4; mnem = power? "st" : "stw"; break; |
1669 |
case PPC_HI6_STWU: wlen=4; mnem = power? "stu" : "stwu"; break; |
case PPC_HI6_STWU: wlen=4; mnem = power? "stu" : "stwu"; break; |
1670 |
case PPC_HI6_STH: wlen=2; mnem = "sth"; break; |
case PPC_HI6_STH: wlen=2; mnem = "sth"; break; |
1673 |
case PPC_HI6_STBU: wlen=1; mnem = "stbu"; break; |
case PPC_HI6_STBU: wlen=1; mnem = "stbu"; break; |
1674 |
case PPC_HI6_LMW: load=1; mnem = power? "lm" : "lmw"; break; |
case PPC_HI6_LMW: load=1; mnem = power? "lm" : "lmw"; break; |
1675 |
case PPC_HI6_STMW: mnem = power? "stm" : "stmw"; break; |
case PPC_HI6_STMW: mnem = power? "stm" : "stmw"; break; |
1676 |
case PPC_HI6_LFD: load=1; fpreg = 1; mnem = "lfd"; break; |
case PPC_HI6_STFD: fpreg=1; wlen=8; mnem = "stfd"; break; |
1677 |
case PPC_HI6_STFD: fpreg = 1; mnem = "stfd"; break; |
case PPC_HI6_STFS: fpreg=1; wlen=4; mnem = "stfs"; break; |
1678 |
} |
} |
1679 |
debug("%s\t", mnem); |
debug("%s\t", mnem); |
1680 |
if (fpreg) |
if (fpreg) |
1685 |
if (!running) |
if (!running) |
1686 |
break; |
break; |
1687 |
addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + imm; |
addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + imm; |
1688 |
|
if (cpu->cd.ppc.bits == 32) |
1689 |
|
addr &= 0xffffffff; |
1690 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1691 |
addr, &offset); |
addr, &offset); |
1692 |
if (symbol != NULL) |
if (symbol != NULL) |
1731 |
int i; |
int i; |
1732 |
for (i=0; i<wlen; i++) |
for (i=0; i<wlen; i++) |
1733 |
tdata |= (cpu->cd.ppc.gpr[rs] & |
tdata |= (cpu->cd.ppc.gpr[rs] & |
1734 |
((uint64_t)0xff << i)); |
((uint64_t)0xff << (i*8))); |
1735 |
debug(": "); |
debug(": "); |
1736 |
if (wlen >= 4) { |
if (wlen >= 4) { |
1737 |
symbol = get_symbol_name(&cpu->machine-> |
symbol = get_symbol_name(&cpu->machine-> |
1739 |
if (symbol != NULL) |
if (symbol != NULL) |
1740 |
debug("%s", symbol); |
debug("%s", symbol); |
1741 |
else |
else |
1742 |
debug("0x%llx", |
debug("0x%llx", (long long)tdata); |
|
(long long)tdata); |
|
1743 |
} else { |
} else { |
1744 |
if (tdata > -256 && tdata < 256) |
if (tdata > -256 && tdata < 256) |
1745 |
debug("%i", (int)tdata); |
debug("%i", (int)tdata); |
1749 |
} |
} |
1750 |
debug(">"); |
debug(">"); |
1751 |
break; |
break; |
1752 |
|
case PPC_HI6_59: |
1753 |
|
xo = (iword >> 1) & 1023; |
1754 |
|
/* NOTE: Some floating point instructions only use the |
1755 |
|
lowest 5 bits of xo, some use all 10 bits! */ |
1756 |
|
switch (xo & 31) { |
1757 |
|
case PPC_59_FDIVS: |
1758 |
|
case PPC_59_FSUBS: |
1759 |
|
case PPC_59_FADDS: |
1760 |
|
case PPC_59_FMULS: |
1761 |
|
case PPC_59_FMADDS: |
1762 |
|
rt = (iword >> 21) & 31; |
1763 |
|
ra = (iword >> 16) & 31; |
1764 |
|
rb = (iword >> 11) & 31; |
1765 |
|
rs = (iword >> 6) & 31; /* actually frc */ |
1766 |
|
rc = iword & 1; |
1767 |
|
switch (xo & 31) { |
1768 |
|
case PPC_59_FDIVS: mnem = "fdivs"; break; |
1769 |
|
case PPC_59_FSUBS: mnem = "fsubs"; break; |
1770 |
|
case PPC_59_FADDS: mnem = "fadds"; break; |
1771 |
|
case PPC_59_FMULS: mnem = "fmuls"; break; |
1772 |
|
case PPC_59_FMADDS: mnem = "fmadds"; break; |
1773 |
|
} |
1774 |
|
debug("%s%s\t", mnem, rc? "." : ""); |
1775 |
|
switch (xo & 31) { |
1776 |
|
case PPC_59_FMULS: |
1777 |
|
debug("f%i,f%i,f%i", rt, ra, rs); |
1778 |
|
break; |
1779 |
|
case PPC_59_FMADDS: |
1780 |
|
debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb); |
1781 |
|
break; |
1782 |
|
default:debug("f%i,f%i,f%i", rt, ra, rb); |
1783 |
|
} |
1784 |
|
break; |
1785 |
|
default:/* TODO: similar to hi6_63 */ |
1786 |
|
debug("unimplemented hi6_59, xo = 0x%x", xo); |
1787 |
|
} |
1788 |
|
break; |
1789 |
case PPC_HI6_63: |
case PPC_HI6_63: |
1790 |
xo = (iword >> 1) & 1023; |
xo = (iword >> 1) & 1023; |
1791 |
switch (xo) { |
/* NOTE: Some floating point instructions only use the |
1792 |
case PPC_63_FMR: |
lowest 5 bits of xo, some use all 10 bits! */ |
1793 |
|
switch (xo & 31) { |
1794 |
|
case PPC_63_FDIV: |
1795 |
|
case PPC_63_FSUB: |
1796 |
|
case PPC_63_FADD: |
1797 |
|
case PPC_63_FMUL: |
1798 |
|
case PPC_63_FMSUB: |
1799 |
|
case PPC_63_FMADD: |
1800 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1801 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
1802 |
rb = (iword >> 11) & 31; |
rb = (iword >> 11) & 31; |
1803 |
|
rs = (iword >> 6) & 31; /* actually frc */ |
1804 |
|
rc = iword & 1; |
1805 |
|
switch (xo & 31) { |
1806 |
|
case PPC_63_FDIV: |
1807 |
|
mnem = power? "fd" : "fdiv"; break; |
1808 |
|
case PPC_63_FSUB: |
1809 |
|
mnem = power? "fs" : "fsub"; break; |
1810 |
|
case PPC_63_FADD: |
1811 |
|
mnem = power? "fa" : "fadd"; break; |
1812 |
|
case PPC_63_FMUL: |
1813 |
|
mnem = power? "fm" : "fmul"; break; |
1814 |
|
case PPC_63_FMSUB: |
1815 |
|
mnem = power? "fms" : "fmsub"; break; |
1816 |
|
case PPC_63_FMADD: |
1817 |
|
mnem = power? "fma" : "fmadd"; break; |
1818 |
|
} |
1819 |
|
debug("%s%s\t", mnem, rc? "." : ""); |
1820 |
|
switch (xo & 31) { |
1821 |
|
case PPC_63_FMUL: |
1822 |
|
debug("f%i,f%i,f%i", rt, ra, rs); |
1823 |
|
break; |
1824 |
|
case PPC_63_FMADD: |
1825 |
|
debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb); |
1826 |
|
break; |
1827 |
|
default:debug("f%i,f%i,f%i", rt, ra, rb); |
1828 |
|
} |
1829 |
|
break; |
1830 |
|
default:rt = (iword >> 21) & 31; |
1831 |
|
ra = (iword >> 16) & 31; |
1832 |
|
rb = (iword >> 11) & 31; |
1833 |
rc = iword & 1; |
rc = iword & 1; |
1834 |
switch (xo) { |
switch (xo) { |
1835 |
|
case PPC_63_FCMPU: |
1836 |
|
case PPC_63_FRSP: |
1837 |
|
case PPC_63_FCTIWZ: |
1838 |
|
case PPC_63_FNEG: |
1839 |
case PPC_63_FMR: |
case PPC_63_FMR: |
1840 |
debug("fmr%s\tf%i,f%i", rc? "." : "", rt, rb); |
case PPC_63_FNABS: |
1841 |
|
case PPC_63_FABS: |
1842 |
|
switch (xo) { |
1843 |
|
case PPC_63_FCMPU: mnem = "fcmpu"; break; |
1844 |
|
case PPC_63_FCTIWZ: |
1845 |
|
mnem = power? "fcirz" : "fctiwz"; break; |
1846 |
|
case PPC_63_FRSP: mnem = "frsp"; break; |
1847 |
|
case PPC_63_FNEG: mnem = "fneg"; break; |
1848 |
|
case PPC_63_FMR: mnem = "fmr"; break; |
1849 |
|
case PPC_63_FNABS: mnem = "fnabs"; break; |
1850 |
|
case PPC_63_FABS: mnem = "fabs"; break; |
1851 |
|
} |
1852 |
|
debug("%s%s\t", mnem, rc? "." : ""); |
1853 |
|
switch (xo) { |
1854 |
|
case PPC_63_FCMPU: |
1855 |
|
debug("%i,f%i,f%i", rt >> 2, ra, rb); |
1856 |
|
break; |
1857 |
|
case PPC_63_FCTIWZ: |
1858 |
|
case PPC_63_FRSP: |
1859 |
|
case PPC_63_FNEG: |
1860 |
|
case PPC_63_FMR: |
1861 |
|
case PPC_63_FNABS: |
1862 |
|
case PPC_63_FABS: |
1863 |
|
debug("f%i,f%i", rt, rb); |
1864 |
|
break; |
1865 |
|
default:debug("f%i,f%i,f%i", rt, ra, rb); |
1866 |
|
} |
1867 |
|
break; |
1868 |
|
case PPC_63_MFFS: |
1869 |
|
debug("mffs%s\tf%i", rc?".":"", rt); |
1870 |
break; |
break; |
1871 |
|
case PPC_63_MTFSF: |
1872 |
|
ra = (iword >> 17) & 255; /* flm */ |
1873 |
|
debug("mtfsf%s\t0x%02x,f%i", rc?".":"", ra, rb); |
1874 |
|
break; |
1875 |
|
default:debug("unimplemented hi6_63, xo = 0x%x", xo); |
1876 |
} |
} |
|
break; |
|
|
default: |
|
|
debug("unimplemented hi6_31, xo = 0x%x", xo); |
|
1877 |
} |
} |
1878 |
break; |
break; |
1879 |
default: |
default: |
1887 |
|
|
1888 |
|
|
1889 |
/* |
/* |
1890 |
|
* debug_spr_usage(): |
1891 |
|
* |
1892 |
|
* Helper function. To speed up overall development speed of the emulator, |
1893 |
|
* all SPR accesses are allowed. This function causes unknown/unimplemented |
1894 |
|
* SPRs to give a warning. |
1895 |
|
*/ |
1896 |
|
static void debug_spr_usage(uint64_t pc, int spr) |
1897 |
|
{ |
1898 |
|
static uint32_t spr_used[1024 / sizeof(uint32_t)]; |
1899 |
|
static int initialized = 0; |
1900 |
|
|
1901 |
|
if (!initialized) { |
1902 |
|
memset(spr_used, 0, sizeof(spr_used)); |
1903 |
|
initialized = 1; |
1904 |
|
} |
1905 |
|
|
1906 |
|
spr &= 1023; |
1907 |
|
if (spr_used[spr >> 2] & (1 << (spr & 3))) |
1908 |
|
return; |
1909 |
|
|
1910 |
|
switch (spr) { |
1911 |
|
/* Known/implemented SPRs: */ |
1912 |
|
case SPR_XER: |
1913 |
|
case SPR_LR: |
1914 |
|
case SPR_CTR: |
1915 |
|
case SPR_DSISR: |
1916 |
|
case SPR_DAR: |
1917 |
|
case SPR_DEC: |
1918 |
|
case SPR_SDR1: |
1919 |
|
case SPR_SRR0: |
1920 |
|
case SPR_SRR1: |
1921 |
|
case SPR_SPRG0: |
1922 |
|
case SPR_SPRG1: |
1923 |
|
case SPR_SPRG2: |
1924 |
|
case SPR_SPRG3: |
1925 |
|
case SPR_PVR: |
1926 |
|
case SPR_DMISS: |
1927 |
|
case SPR_DCMP: |
1928 |
|
case SPR_HASH1: |
1929 |
|
case SPR_HASH2: |
1930 |
|
case SPR_IMISS: |
1931 |
|
case SPR_ICMP: |
1932 |
|
case SPR_DBSR: |
1933 |
|
case SPR_PIR: |
1934 |
|
break; |
1935 |
|
default:if (spr >= SPR_IBAT0U && spr <= SPR_DBAT3L) { |
1936 |
|
break; |
1937 |
|
} else |
1938 |
|
fatal("[ using UNIMPLEMENTED spr %i (%s), pc = " |
1939 |
|
"0x%llx ]\n", spr, ppc_spr_names[spr] == NULL? |
1940 |
|
"UNKNOWN" : ppc_spr_names[spr], (long long)pc); |
1941 |
|
} |
1942 |
|
|
1943 |
|
spr_used[spr >> 2] |= (1 << (spr & 3)); |
1944 |
|
} |
1945 |
|
|
1946 |
|
|
1947 |
|
/* |
1948 |
* update_cr0(): |
* update_cr0(): |
1949 |
* |
* |
1950 |
* Sets the top 4 bits of the CR register. |
* Sets the top 4 bits of the CR register. |
1970 |
} |
} |
1971 |
|
|
1972 |
/* SO bit, copied from XER: */ |
/* SO bit, copied from XER: */ |
1973 |
c |= ((cpu->cd.ppc.xer >> 31) & 1); |
c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1); |
1974 |
|
|
1975 |
cpu->cd.ppc.cr &= ~((uint32_t)0xf << 28); |
cpu->cd.ppc.cr &= ~((uint32_t)0xf << 28); |
1976 |
cpu->cd.ppc.cr |= ((uint32_t)c << 28); |
cpu->cd.ppc.cr |= ((uint32_t)c << 28); |
1982 |
|
|
1983 |
#include "tmp_ppc_tail.c" |
#include "tmp_ppc_tail.c" |
1984 |
|
|
1985 |
|
|