25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips_coproc.c,v 1.2 2005/09/11 10:37:37 debug Exp $ |
* $Id: cpu_mips_coproc.c,v 1.3 2005/10/26 14:37:03 debug Exp $ |
29 |
* |
* |
30 |
* Emulation of MIPS coprocessors. |
* Emulation of MIPS coprocessors. |
31 |
*/ |
*/ |
93 |
/* Default values: */ |
/* Default values: */ |
94 |
c->reg[COP0_CONFIG] = |
c->reg[COP0_CONFIG] = |
95 |
( 0 << 31) /* config1 present */ |
( 0 << 31) /* config1 present */ |
96 |
| (0x00 << 16) /* implementation dependant */ |
| (0x00 << 16) /* implementation dependent */ |
97 |
| ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15) |
| ((cpu->byte_order==EMUL_BIG_ENDIAN? 1 : 0) << 15) |
98 |
/* endian mode */ |
/* endian mode */ |
99 |
| ( 2 << 13) /* 0 = MIPS32, |
| ( 2 << 13) /* 0 = MIPS32, |