1 |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
6 |
* |
7 |
* 1. Redistributions of source code must retain the above copyright |
8 |
* notice, this list of conditions and the following disclaimer. |
9 |
* 2. Redistributions in binary form must reproduce the above copyright |
10 |
* notice, this list of conditions and the following disclaimer in the |
11 |
* documentation and/or other materials provided with the distribution. |
12 |
* 3. The name of the author may not be used to endorse or promote products |
13 |
* derived from this software without specific prior written permission. |
14 |
* |
15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
26 |
* |
27 |
* |
28 |
* $Id: cpu_ia64.c,v 1.13 2006/07/16 13:32:26 debug Exp $ |
29 |
* |
30 |
* IA64 CPU emulation. |
31 |
* |
32 |
* TODO: Everything. |
33 |
*/ |
34 |
|
35 |
#include <stdio.h> |
36 |
#include <stdlib.h> |
37 |
#include <string.h> |
38 |
#include <ctype.h> |
39 |
|
40 |
#include "cpu.h" |
41 |
#include "machine.h" |
42 |
#include "memory.h" |
43 |
#include "misc.h" |
44 |
#include "symbol.h" |
45 |
|
46 |
#include "tmp_ia64_head.c" |
47 |
|
48 |
|
49 |
/* |
50 |
* ia64_cpu_new(): |
51 |
* |
52 |
* Create a new IA64 CPU object by filling the CPU struct. |
53 |
* Return 1 on success, 0 if cpu_type_name isn't a valid IA64 processor. |
54 |
*/ |
55 |
int ia64_cpu_new(struct cpu *cpu, struct memory *mem, |
56 |
struct machine *machine, int cpu_id, char *cpu_type_name) |
57 |
{ |
58 |
if (strcasecmp(cpu_type_name, "IA64") != 0) |
59 |
return 0; |
60 |
|
61 |
cpu->run_instr = ia64_run_instr; |
62 |
cpu->memory_rw = ia64_memory_rw; |
63 |
cpu->update_translation_table = ia64_update_translation_table; |
64 |
cpu->invalidate_translation_caches = |
65 |
ia64_invalidate_translation_caches; |
66 |
cpu->invalidate_code_translation = ia64_invalidate_code_translation; |
67 |
cpu->is_32bit = 0; |
68 |
|
69 |
/* Only show name and caches etc for CPU nr 0: */ |
70 |
if (cpu_id == 0) { |
71 |
debug("%s", cpu->name); |
72 |
} |
73 |
|
74 |
return 1; |
75 |
} |
76 |
|
77 |
|
78 |
/* |
79 |
* ia64_cpu_dumpinfo(): |
80 |
*/ |
81 |
void ia64_cpu_dumpinfo(struct cpu *cpu) |
82 |
{ |
83 |
/* TODO */ |
84 |
debug("\n"); |
85 |
} |
86 |
|
87 |
|
88 |
/* |
89 |
* ia64_cpu_list_available_types(): |
90 |
* |
91 |
* Print a list of available IA64 CPU types. |
92 |
*/ |
93 |
void ia64_cpu_list_available_types(void) |
94 |
{ |
95 |
/* TODO */ |
96 |
|
97 |
debug("IA64\n"); |
98 |
} |
99 |
|
100 |
|
101 |
/* |
102 |
* ia64_cpu_register_match(): |
103 |
*/ |
104 |
void ia64_cpu_register_match(struct machine *m, char *name, |
105 |
int writeflag, uint64_t *valuep, int *match_register) |
106 |
{ |
107 |
int cpunr = 0; |
108 |
|
109 |
/* CPU number: */ |
110 |
|
111 |
/* TODO */ |
112 |
|
113 |
if (strcasecmp(name, "pc") == 0) { |
114 |
if (writeflag) { |
115 |
m->cpus[cpunr]->pc = *valuep; |
116 |
} else |
117 |
*valuep = m->cpus[cpunr]->pc; |
118 |
*match_register = 1; |
119 |
} |
120 |
|
121 |
/* TODO */ |
122 |
} |
123 |
|
124 |
|
125 |
/* |
126 |
* ia64_cpu_register_dump(): |
127 |
* |
128 |
* Dump cpu registers in a relatively readable format. |
129 |
* |
130 |
* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
131 |
* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
132 |
*/ |
133 |
void ia64_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
134 |
{ |
135 |
char *symbol; |
136 |
uint64_t offset; |
137 |
int x = cpu->cpu_id; |
138 |
|
139 |
if (gprs) { |
140 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
141 |
cpu->pc, &offset); |
142 |
debug("cpu%i:\t pc = 0x%016"PRIx64, x, (uint64_t)cpu->pc); |
143 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
144 |
|
145 |
/* TODO */ |
146 |
} |
147 |
} |
148 |
|
149 |
|
150 |
/* |
151 |
* mips_cpu_tlbdump(): |
152 |
* |
153 |
* Called from the debugger to dump the TLB in a readable format. |
154 |
* x is the cpu number to dump, or -1 to dump all CPUs. |
155 |
* |
156 |
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
157 |
* just dumped. |
158 |
*/ |
159 |
void ia64_cpu_tlbdump(struct machine *m, int x, int rawflag) |
160 |
{ |
161 |
} |
162 |
|
163 |
|
164 |
/* |
165 |
* ia64_cpu_gdb_stub(): |
166 |
* |
167 |
* Execute a "remote GDB" command. Returns a newly allocated response string |
168 |
* on success, NULL on failure. |
169 |
*/ |
170 |
char *ia64_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
171 |
{ |
172 |
fatal("ia64_cpu_gdb_stub(): TODO\n"); |
173 |
return NULL; |
174 |
} |
175 |
|
176 |
|
177 |
/* |
178 |
* ia64_cpu_interrupt(): |
179 |
*/ |
180 |
int ia64_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
181 |
{ |
182 |
fatal("ia64_cpu_interrupt(): TODO\n"); |
183 |
return 0; |
184 |
} |
185 |
|
186 |
|
187 |
/* |
188 |
* ia64_cpu_interrupt_ack(): |
189 |
*/ |
190 |
int ia64_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
191 |
{ |
192 |
/* fatal("ia64_cpu_interrupt_ack(): TODO\n"); */ |
193 |
return 0; |
194 |
} |
195 |
|
196 |
|
197 |
/* |
198 |
* ia64_cpu_disassemble_instr(): |
199 |
* |
200 |
* Convert an instruction word into human readable format, for instruction |
201 |
* tracing. |
202 |
* |
203 |
* If running is 1, cpu->pc should be the address of the instruction. |
204 |
* |
205 |
* If running is 0, things that depend on the runtime environment (eg. |
206 |
* register contents) will not be shown, and addr will be used instead of |
207 |
* cpu->pc for relative addresses. |
208 |
*/ |
209 |
int ia64_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
210 |
int running, uint64_t dumpaddr) |
211 |
{ |
212 |
uint64_t offset; |
213 |
char *symbol; |
214 |
|
215 |
if (running) |
216 |
dumpaddr = cpu->pc; |
217 |
|
218 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
219 |
dumpaddr, &offset); |
220 |
if (symbol != NULL && offset == 0) |
221 |
debug("<%s>\n", symbol); |
222 |
|
223 |
if (cpu->machine->ncpus > 1 && running) |
224 |
debug("cpu%i:\t", cpu->cpu_id); |
225 |
|
226 |
debug("%016"PRIx64": ", (uint64_t) dumpaddr); |
227 |
|
228 |
debug("TODO\n"); |
229 |
|
230 |
/* iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); */ |
231 |
|
232 |
return 16; |
233 |
} |
234 |
|
235 |
|
236 |
#include "tmp_ia64_tail.c" |
237 |
|