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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT HPPAALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_hppa.c,v 1.1 2005/09/07 07:10:16 debug Exp $ |
* $Id: cpu_hppa.c,v 1.13 2006/06/16 18:31:25 debug Exp $ |
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* |
* |
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* HP PA-RISC CPU emulation. |
* HP PA-RISC CPU emulation. |
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* |
* |
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if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
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cpu->update_translation_table = hppa32_update_translation_table; |
cpu->update_translation_table = hppa32_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
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hppa32_invalidate_translation_caches_paddr; |
hppa32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
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hppa32_invalidate_code_translation; |
hppa32_invalidate_code_translation; |
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} else { |
} else { |
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cpu->update_translation_table = hppa_update_translation_table; |
cpu->update_translation_table = hppa_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
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hppa_invalidate_translation_caches_paddr; |
hppa_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
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hppa_invalidate_code_translation; |
hppa_invalidate_code_translation; |
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} |
} |
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/* Only hppaow name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
if (cpu_id == 0) { |
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debug("%s", cpu->name); |
debug("%s", cpu->name); |
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} |
} |
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hppa_init_64bit_dummy_tables(cpu); |
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return 1; |
return 1; |
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} |
} |
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void hppa_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
void hppa_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
{ |
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char *symbol; |
char *symbol; |
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uint64_t offset, tmp; |
uint64_t offset; |
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int i, x = cpu->cpu_id, nregs = 32; |
int i, x = cpu->cpu_id, nregs = 32; |
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int bits32 = cpu->cd.hppa.bits == 32; |
int bits32 = cpu->cd.hppa.bits == 32; |
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debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
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if (bits32) |
if (bits32) |
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debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t) cpu->pc); |
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else |
else |
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debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t) cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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if (bits32) { |
if (bits32) { |
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for (i=0; i<nregs; i++) { |
for (i=0; i<nregs; i++) { |
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if ((i % 4) == 0) |
if ((i % 4) == 0) |
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debug("cpu%i:", x); |
debug("cpu%i:", x); |
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debug(" r%02i = 0x%08x ", i, |
debug(" r%02i = 0x%08"PRIx32" ", i, |
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(int)cpu->cd.hppa.r[i]); |
(uint32_t)cpu->cd.hppa.r[i]); |
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if ((i % 4) == 3) |
if ((i % 4) == 3) |
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debug("\n"); |
debug("\n"); |
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} |
} |
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int r = (i >> 1) + ((i & 1) << 4); |
int r = (i >> 1) + ((i & 1) << 4); |
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if ((i % 2) == 0) |
if ((i % 2) == 0) |
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debug("cpu%i:", x); |
debug("cpu%i:", x); |
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debug(" r%02i = 0x%016llx ", r, |
debug(" r%02i = 0x%016"PRIx64" ", r, |
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(long long)cpu->cd.hppa.r[r]); |
(uint64_t) cpu->cd.hppa.r[r]); |
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if ((i % 2) == 1) |
if ((i % 2) == 1) |
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debug("\n"); |
debug("\n"); |
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} |
} |
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/* |
/* |
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* hppa_cpu_show_full_statistics(): |
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* |
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* Show detailed statistics on opcode usage on each cpu. |
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*/ |
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void hppa_cpu_show_full_statistics(struct machine *m) |
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{ |
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fatal("hppa_cpu_show_full_statistics(): TODO\n"); |
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} |
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/* |
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* hppa_cpu_tlbdump(): |
* hppa_cpu_tlbdump(): |
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* |
* |
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* Called from the debugger to dump the TLB in a readable format. |
* Called from the debugger to dump the TLB in a readable format. |
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*/ |
*/ |
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void hppa_cpu_tlbdump(struct machine *m, int x, int rawflag) |
void hppa_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
{ |
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fatal("hppa_cpu_tlbdump(): TODO\n"); |
} |
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/* |
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* hppa_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *hppa_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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fatal("hppa_cpu_gdb_stub(): TODO\n"); |
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return NULL; |
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} |
} |
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* Convert an instruction word into human readable format, for instruction |
* Convert an instruction word into human readable format, for instruction |
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* tracing. |
* tracing. |
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* |
* |
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* If running is 1, cpu->pc hppaould be the address of the instruction. |
* If running is 1, cpu->pc should be the address of the instruction. |
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* |
* |
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* If running is 0, things that depend on the runtime environment (eg. |
* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be hppaown, and addr will be used instead of |
* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
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*/ |
*/ |
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int hppa_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int hppa_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
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int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
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{ |
{ |
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uint64_t offset, addr; |
uint64_t offset; |
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uint32_t iword; |
uint32_t iword; |
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int hi6; |
char *symbol; |
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char *symbol, *mnem = "ERROR"; |
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if (running) |
if (running) |
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dumpaddr = cpu->pc; |
dumpaddr = cpu->pc; |
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debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
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if (cpu->cd.hppa.bits == 32) |
if (cpu->cd.hppa.bits == 32) |
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debug("%08x", (int)dumpaddr); |
debug("%08"PRIx32, (uint32_t) dumpaddr); |
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else |
else |
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debug("%016llx", (long long)dumpaddr); |
debug("%016"PRIx64, (uint64_t) dumpaddr); |
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if (cpu->byte_order == EMUL_BIG_ENDIAN) |
if (cpu->byte_order == EMUL_BIG_ENDIAN) |
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iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
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iword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8) |
iword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8) |
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+ instr[0]; |
+ instr[0]; |
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debug(": %08x\t", iword); |
debug(": %08"PRIx32"\t", (uint32_t) iword); |
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/* |
/* |
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* Decode the instruction: |
* Decode the instruction: |