25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_dyntrans.c,v 1.113 2006/07/21 20:09:15 debug Exp $ |
* $Id: cpu_dyntrans.c,v 1.132 2006/10/27 13:12:20 debug Exp $ |
29 |
* |
* |
30 |
* Common dyntrans routines. Included from cpu_*.c. |
* Common dyntrans routines. Included from cpu_*.c. |
31 |
*/ |
*/ |
45 |
int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t) |
int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t) |
46 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC); |
cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC); |
47 |
|
|
48 |
|
if (cpu->machine->statistics_file == NULL) { |
49 |
|
fatal("statistics gathering with no filename set is" |
50 |
|
" meaningless\n"); |
51 |
|
return; |
52 |
|
} |
53 |
|
|
54 |
buf[0] = '\0'; |
buf[0] = '\0'; |
55 |
|
|
56 |
while ((ch = cpu->machine->statistics_fields[i]) != '\0') { |
while ((ch = cpu->machine->statistics_fields[i]) != '\0') { |
229 |
#endif |
#endif |
230 |
#ifdef DYNTRANS_PPC |
#ifdef DYNTRANS_PPC |
231 |
if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) { |
232 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
if (!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) |
233 |
|
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
234 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
235 |
} |
} |
236 |
if (cpu->cd.ppc.irq_asserted && cpu->cd.ppc.msr & PPC_MSR_EE) |
if (cpu->cd.ppc.irq_asserted && cpu->cd.ppc.msr & PPC_MSR_EE) |
237 |
ppc_exception(cpu, PPC_EXCEPTION_EI); |
ppc_exception(cpu, PPC_EXCEPTION_EI); |
238 |
#endif |
#endif |
239 |
|
#ifdef DYNTRANS_SH |
240 |
|
if (cpu->cd.sh.int_to_assert > 0 && !(cpu->cd.sh.sr & SH_SR_BL) |
241 |
|
&& ((cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT) |
242 |
|
< cpu->cd.sh.int_level) |
243 |
|
sh_exception(cpu, 0, cpu->cd.sh.int_to_assert, 0); |
244 |
|
#endif |
245 |
|
|
246 |
cached_pc = cpu->pc; |
cached_pc = cpu->pc; |
247 |
|
|
248 |
cpu->n_translated_instrs = 0; |
cpu->n_translated_instrs = 0; |
|
cpu->running_translated = 1; |
|
249 |
|
|
250 |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
251 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
261 |
cpu_register_dump(cpu->machine, cpu, 1, 0x1); |
cpu_register_dump(cpu->machine, cpu, 1, 0x1); |
262 |
} |
} |
263 |
if (cpu->machine->instruction_trace) { |
if (cpu->machine->instruction_trace) { |
264 |
|
/* TODO/Note: This must be large enough to hold |
265 |
|
any instruction for any ISA: */ |
266 |
|
unsigned char instr[1 << |
267 |
|
DYNTRANS_INSTR_ALIGNMENT_SHIFT]; |
268 |
#ifdef DYNTRANS_X86 |
#ifdef DYNTRANS_X86 |
|
unsigned char instr[17]; |
|
269 |
cpu->cd.x86.cursegment = X86_S_CS; |
cpu->cd.x86.cursegment = X86_S_CS; |
270 |
cpu->cd.x86.seg_override = 0; |
cpu->cd.x86.seg_override = 0; |
|
#else |
|
|
#ifdef DYNTRANS_M68K |
|
|
unsigned char instr[16]; /* TODO: 16? */ |
|
|
#else |
|
|
unsigned char instr[4]; /* General case... */ |
|
271 |
#endif |
#endif |
|
#endif |
|
|
|
|
272 |
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
273 |
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
274 |
fatal("XXX_run_instr(): could not read " |
fatal("XXX_run_instr(): could not read " |
275 |
"the instruction\n"); |
"the instruction\n"); |
276 |
} else { |
} else { |
277 |
cpu_disassemble_instr(cpu->machine, cpu, |
#ifdef DYNTRANS_DELAYSLOT |
278 |
instr, 1, 0); |
int len = |
279 |
|
#endif |
280 |
|
cpu_disassemble_instr( |
281 |
|
cpu->machine, cpu, instr, 1, 0); |
282 |
#ifdef DYNTRANS_DELAYSLOT |
#ifdef DYNTRANS_DELAYSLOT |
283 |
/* Show the instruction in the delay slot, |
/* Show the instruction in the delay slot, |
284 |
if any: */ |
if any: */ |
289 |
instr)) { |
instr)) { |
290 |
int saved_delayslot = cpu->delay_slot; |
int saved_delayslot = cpu->delay_slot; |
291 |
cpu->memory_rw(cpu, cpu->mem, cached_pc |
cpu->memory_rw(cpu, cpu->mem, cached_pc |
292 |
+ sizeof(instr), &instr[0], |
+ len, &instr[0], |
293 |
sizeof(instr), MEM_READ, |
sizeof(instr), MEM_READ, |
294 |
CACHE_INSTRUCTION); |
CACHE_INSTRUCTION); |
295 |
cpu->delay_slot = DELAYED; |
cpu->delay_slot = DELAYED; |
296 |
cpu->pc += sizeof(instr); |
cpu->pc += len; |
297 |
cpu_disassemble_instr(cpu->machine, |
cpu_disassemble_instr(cpu->machine, |
298 |
cpu, instr, 1, 0); |
cpu, instr, 1, 0); |
299 |
cpu->delay_slot = saved_delayslot; |
cpu->delay_slot = saved_delayslot; |
300 |
cpu->pc -= sizeof(instr); |
cpu->pc -= len; |
301 |
} |
} |
302 |
#endif |
#endif |
303 |
} |
} |
304 |
} |
} |
305 |
|
|
|
/* When single-stepping, multiple instruction calls cannot |
|
|
be combined into one. This clears all translations: */ |
|
|
if (cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & COMBINATIONS) { |
|
|
int i; |
|
|
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) { |
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->ics[i].f = |
|
|
#ifdef DYNTRANS_DUALMODE_32 |
|
|
cpu->is_32bit? |
|
|
instr32(to_be_translated) : |
|
|
#endif |
|
|
instr(to_be_translated); |
|
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->ics[i]. |
|
|
arg[0] = 0; |
|
|
#endif |
|
|
} |
|
|
|
|
|
fatal("[ Note: The translation of physical page 0x%" |
|
|
PRIx64" contained combinations of instructions; " |
|
|
"these are now flushed because we are single-" |
|
|
"stepping. ]\n", (long long)cpu->cd.DYNTRANS_ARCH. |
|
|
cur_physpage->physaddr); |
|
|
|
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags &= |
|
|
~COMBINATIONS; |
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->translations = 0; |
|
|
} |
|
|
|
|
306 |
if (cpu->machine->statistics_enabled) |
if (cpu->machine->statistics_enabled) |
307 |
S; |
S; |
308 |
|
|
327 |
cpu->machine->tick_func[1](cpu, cpu->machine->tick_extra[1]); |
cpu->machine->tick_func[1](cpu, cpu->machine->tick_extra[1]); |
328 |
/* printf("B\n"); */ |
/* printf("B\n"); */ |
329 |
|
|
330 |
if (!cpu->running_translated || |
if (n_instrs + cpu->n_translated_instrs >= |
|
n_instrs + cpu->n_translated_instrs >= |
|
331 |
N_SAFE_DYNTRANS_LIMIT) |
N_SAFE_DYNTRANS_LIMIT) |
332 |
break; |
break; |
333 |
} |
} |
344 |
|
|
345 |
n_instrs += 24; |
n_instrs += 24; |
346 |
|
|
347 |
if (!cpu->running_translated || |
if (n_instrs + cpu->n_translated_instrs >= |
|
n_instrs + cpu->n_translated_instrs >= |
|
348 |
N_SAFE_DYNTRANS_LIMIT) |
N_SAFE_DYNTRANS_LIMIT) |
349 |
break; |
break; |
350 |
} |
} |
351 |
} else { |
} else { |
352 |
/* Execute multiple instructions: */ |
/* Execute multiple instructions: */ |
353 |
n_instrs = 0; |
int n = 0; |
354 |
for (;;) { |
for (;;) { |
355 |
struct DYNTRANS_IC *ic; |
struct DYNTRANS_IC *ic; |
356 |
|
|
362 |
|
|
363 |
I; I; I; I; I; I; I; I; I; I; |
I; I; I; I; I; I; I; I; I; I; |
364 |
|
|
365 |
n_instrs += 60; |
n += 60; |
366 |
|
|
367 |
if (!cpu->running_translated || |
if (n + cpu->n_translated_instrs >= |
|
n_instrs + cpu->n_translated_instrs >= |
|
368 |
N_SAFE_DYNTRANS_LIMIT) |
N_SAFE_DYNTRANS_LIMIT) |
369 |
break; |
break; |
370 |
} |
} |
371 |
|
n_instrs = n; |
372 |
} |
} |
373 |
|
|
374 |
n_instrs += cpu->n_translated_instrs; |
n_instrs += cpu->n_translated_instrs; |
405 |
(int32_t) (old + n_instrs); |
(int32_t) (old + n_instrs); |
406 |
diff2 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - |
diff2 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - |
407 |
cpu->cd.mips.coproc[0]->reg[COP0_COUNT]; |
cpu->cd.mips.coproc[0]->reg[COP0_COUNT]; |
408 |
if (cpu->cd.mips.compare_register_set && diff1>0 && diff2<=0) |
|
409 |
cpu_interrupt(cpu, 7); |
if (cpu->cd.mips.compare_register_set) { |
410 |
|
#if 1 |
411 |
|
/* Not yet. TODO */ |
412 |
|
if (cpu->machine->emulated_hz > 0) { |
413 |
|
if (cpu->cd.mips.compare_interrupts_pending > 0) |
414 |
|
cpu_interrupt(cpu, 7); |
415 |
|
} else |
416 |
|
#endif |
417 |
|
{ |
418 |
|
if (diff1 > 0 && diff2 <= 0) |
419 |
|
cpu_interrupt(cpu, 7); |
420 |
|
} |
421 |
|
} |
422 |
} |
} |
423 |
#endif |
#endif |
424 |
#ifdef DYNTRANS_PPC |
#ifdef DYNTRANS_PPC |
461 |
6 |
6 |
462 |
#else |
#else |
463 |
#ifdef DYNTRANS_SH |
#ifdef DYNTRANS_SH |
464 |
8 |
8 /* Both for 32-bit and 64-bit SuperH */ |
465 |
#else |
#else |
466 |
4 /* Default value for most archs */ |
4 /* Default value for most archs */ |
467 |
#endif |
#endif |
502 |
they go downwards, ie. 22,23 and so on */ |
they go downwards, ie. 22,23 and so on */ |
503 |
r[24 |
r[24 |
504 |
#endif |
#endif |
505 |
|
#ifdef DYNTRANS_AVR32 |
506 |
|
r[0 /* TODO */ |
507 |
|
#endif |
508 |
#ifdef DYNTRANS_HPPA |
#ifdef DYNTRANS_HPPA |
509 |
r[0 /* TODO */ |
r[0 /* TODO */ |
510 |
#endif |
#endif |
523 |
#ifdef DYNTRANS_PPC |
#ifdef DYNTRANS_PPC |
524 |
gpr[3 |
gpr[3 |
525 |
#endif |
#endif |
526 |
|
#ifdef DYNTRANS_RCA180X |
527 |
|
r[0 /* TODO */ |
528 |
|
#endif |
529 |
#ifdef DYNTRANS_SH |
#ifdef DYNTRANS_SH |
530 |
r[2 |
r[4 /* NetBSD seems to use 4? But 2 seems |
531 |
|
to be used by other code? TODO */ |
532 |
#endif |
#endif |
533 |
#ifdef DYNTRANS_SPARC |
#ifdef DYNTRANS_SPARC |
534 |
r[24 |
r[8 /* o0..o5 */ |
535 |
#endif |
#endif |
536 |
+ x]; |
+ x]; |
537 |
#endif |
#endif |
650 |
if (!ok) { |
if (!ok) { |
651 |
uint64_t paddr; |
uint64_t paddr; |
652 |
if (cpu->translate_v2p != NULL) { |
if (cpu->translate_v2p != NULL) { |
653 |
|
uint64_t vaddr = |
654 |
|
#if defined(MODE32) && defined(DYNTRANS_MIPS) |
655 |
|
/* 32-bit MIPS is _sign_ extend, not zero. */ |
656 |
|
(int32_t) |
657 |
|
#endif |
658 |
|
cached_pc; |
659 |
ok = cpu->translate_v2p( |
ok = cpu->translate_v2p( |
660 |
cpu, cached_pc, &paddr, FLAG_INSTR); |
cpu, vaddr, &paddr, FLAG_INSTR); |
661 |
} else { |
} else { |
662 |
paddr = cached_pc; |
paddr = cached_pc; |
663 |
ok = 1; |
ok = 1; |
908 |
} |
} |
909 |
|
|
910 |
ppp->next_ofs = 0; |
ppp->next_ofs = 0; |
|
ppp->flags = 0; |
|
911 |
ppp->translations = 0; |
ppp->translations = 0; |
912 |
/* ppp->physaddr is filled in by the page allocator */ |
/* ppp->physaddr is filled in by the page allocator */ |
913 |
|
|
1317 |
x >>= 1; |
x >>= 1; |
1318 |
} |
} |
1319 |
|
|
|
ppp->flags &= ~COMBINATIONS; |
|
1320 |
ppp->translations = 0; |
ppp->translations = 0; |
1321 |
} |
} |
1322 |
#endif |
#endif |
1371 |
void DYNTRANS_UPDATE_TRANSLATION_TABLE(struct cpu *cpu, uint64_t vaddr_page, |
void DYNTRANS_UPDATE_TRANSLATION_TABLE(struct cpu *cpu, uint64_t vaddr_page, |
1372 |
unsigned char *host_page, int writeflag, uint64_t paddr_page) |
unsigned char *host_page, int writeflag, uint64_t paddr_page) |
1373 |
{ |
{ |
1374 |
#ifndef MODE32 |
int found, r, useraccess = 0; |
|
int64_t lowest, highest = -1; |
|
|
#endif |
|
|
int found, r, lowest_index, useraccess = 0; |
|
1375 |
|
|
1376 |
#ifdef MODE32 |
#ifdef MODE32 |
1377 |
uint32_t index; |
uint32_t index; |
1402 |
} |
} |
1403 |
|
|
1404 |
/* Scan the current TLB entries: */ |
/* Scan the current TLB entries: */ |
|
lowest_index = 0; |
|
1405 |
|
|
1406 |
#ifdef MODE32 |
#ifdef MODE32 |
1407 |
/* |
/* |
1414 |
*/ |
*/ |
1415 |
found = (int)cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[ |
found = (int)cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[ |
1416 |
DYNTRANS_ADDR_TO_PAGENR(vaddr_page)] - 1; |
DYNTRANS_ADDR_TO_PAGENR(vaddr_page)] - 1; |
|
if (found < 0) { |
|
|
static unsigned int x = 0; |
|
|
lowest_index = (x++) % DYNTRANS_MAX_VPH_TLB_ENTRIES; |
|
|
} |
|
1417 |
#else |
#else |
1418 |
lowest = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[0].timestamp; |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1419 |
found = -1; |
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
1420 |
for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) { |
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
1421 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp < lowest) { |
& mask3; |
1422 |
lowest = cpu->cd.DYNTRANS_ARCH. |
|
1423 |
vph_tlb_entry[r].timestamp; |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1424 |
lowest_index = r; |
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) |
1425 |
} |
found = -1; |
1426 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp > highest) |
else { |
1427 |
highest = cpu->cd.DYNTRANS_ARCH. |
l3 = l2->l3[x2]; |
1428 |
vph_tlb_entry[r].timestamp; |
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) |
1429 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && |
found = -1; |
1430 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page == |
else |
1431 |
vaddr_page) { |
found = (int)l3->vaddr_to_tlbindex[x3] - 1; |
|
found = r; |
|
|
break; |
|
|
} |
|
1432 |
} |
} |
1433 |
#endif |
#endif |
1434 |
|
|
1435 |
if (found < 0) { |
if (found < 0) { |
1436 |
/* Create the new TLB entry, overwriting the oldest one: */ |
/* Create the new TLB entry, overwriting a "random" entry: */ |
1437 |
r = lowest_index; |
static unsigned int x = 0; |
1438 |
|
r = (x++) % DYNTRANS_MAX_VPH_TLB_ENTRIES; |
1439 |
|
|
1440 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
1441 |
/* This one has to be invalidated first: */ |
/* This one has to be invalidated first: */ |
1442 |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, |
1450 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page = vaddr_page; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page = vaddr_page; |
1451 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = |
1452 |
writeflag & MEM_WRITE; |
writeflag & MEM_WRITE; |
|
#ifndef MODE32 |
|
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp = highest + 1; |
|
|
#endif |
|
1453 |
|
|
1454 |
/* Add the new translation to the table: */ |
/* Add the new translation to the table: */ |
1455 |
#ifdef MODE32 |
#ifdef MODE32 |
1466 |
|= 1 << (index & 31); |
|= 1 << (index & 31); |
1467 |
#endif |
#endif |
1468 |
#else /* !MODE32 */ |
#else /* !MODE32 */ |
|
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
|
|
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
|
|
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
|
|
& mask3; |
|
|
|
|
1469 |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1470 |
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) { |
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) { |
1471 |
if (cpu->cd.DYNTRANS_ARCH.next_free_l2 != NULL) { |
if (cpu->cd.DYNTRANS_ARCH.next_free_l2 != NULL) { |
1550 |
* Writeflag = MEM_DOWNGRADE: Downgrade to readonly. |
* Writeflag = MEM_DOWNGRADE: Downgrade to readonly. |
1551 |
*/ |
*/ |
1552 |
r = found; |
r = found; |
|
#ifndef MODE32 |
|
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp = highest + 1; |
|
|
#endif |
|
1553 |
if (writeflag & MEM_WRITE) |
if (writeflag & MEM_WRITE) |
1554 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1; |
1555 |
if (writeflag & MEM_DOWNGRADE) |
if (writeflag & MEM_DOWNGRADE) |
1698 |
#ifdef DYNTRANS_DELAYSLOT |
#ifdef DYNTRANS_DELAYSLOT |
1699 |
&& !in_crosspage_delayslot |
&& !in_crosspage_delayslot |
1700 |
#endif |
#endif |
1701 |
) { |
&& cpu->cd.DYNTRANS_ARCH.combination_check != NULL |
1702 |
if (cpu->cd.DYNTRANS_ARCH.combination_check != NULL && |
&& cpu->machine->allow_instruction_combinations) { |
1703 |
cpu->machine->allow_instruction_combinations) |
cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic, |
1704 |
cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic, |
addr & (DYNTRANS_PAGESIZE - 1)); |
|
addr & (DYNTRANS_PAGESIZE - 1)); |
|
1705 |
} |
} |
1706 |
|
|
1707 |
cpu->cd.DYNTRANS_ARCH.combination_check = NULL; |
cpu->cd.DYNTRANS_ARCH.combination_check = NULL; |
1781 |
} |
} |
1782 |
|
|
1783 |
cpu->running = 0; |
cpu->running = 0; |
1784 |
cpu->dead = 1; |
|
1785 |
|
/* Note: Single-stepping can jump here. */ |
1786 |
stop_running_translated: |
stop_running_translated: |
1787 |
|
|
1788 |
debugger_n_steps_left_before_interaction = 0; |
debugger_n_steps_left_before_interaction = 0; |
1789 |
cpu->running_translated = 0; |
|
1790 |
ic = cpu->cd.DYNTRANS_ARCH.next_ic = ¬hing_call; |
ic = cpu->cd.DYNTRANS_ARCH.next_ic = ¬hing_call; |
1791 |
cpu->cd.DYNTRANS_ARCH.next_ic ++; |
cpu->cd.DYNTRANS_ARCH.next_ic ++; |
1792 |
|
|
1793 |
/* Execute the "nothing" instruction: */ |
/* Execute the "nothing" instruction: */ |
1794 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
1795 |
|
|
1796 |
#endif /* DYNTRANS_TO_BE_TRANSLATED_TAIL */ |
#endif /* DYNTRANS_TO_BE_TRANSLATED_TAIL */ |
1797 |
|
|