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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
28 |
* $Id: cpu_dyntrans.c,v 1.27 2005/10/27 14:01:13 debug Exp $ |
* $Id: cpu_dyntrans.c,v 1.147 2007/04/19 15:18:16 debug Exp $ |
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* |
* |
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* Common dyntrans routines. Included from cpu_*.c. |
* Common dyntrans routines. Included from cpu_*.c. |
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*/ |
*/ |
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#ifdef DYNTRANS_CPU_RUN_INSTR |
#ifndef STATIC_STUFF |
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#define STATIC_STUFF |
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/* |
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* gather_statistics(): |
38 |
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*/ |
39 |
static void gather_statistics(struct cpu *cpu) |
static void gather_statistics(struct cpu *cpu) |
40 |
{ |
{ |
41 |
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char ch, buf[60]; |
42 |
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struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic; |
43 |
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int i = 0; |
44 |
uint64_t a; |
uint64_t a; |
45 |
int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t) |
int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t) |
46 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC); |
cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC); |
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if (low_pc < 0 || low_pc >= DYNTRANS_IC_ENTRIES_PER_PAGE) |
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return; |
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#if 1 |
if (cpu->machine->statistics_file == NULL) { |
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/* Use the physical address: */ |
fatal("statistics gathering with no filename set is" |
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cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
" meaningless\n"); |
51 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
return; |
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a = cpu->cd.DYNTRANS_ARCH.cur_physpage->physaddr; |
} |
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#else |
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/* Use the PC (virtual address): */ |
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a = cpu->pc; |
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#endif |
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a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
buf[0] = '\0'; |
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DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
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a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT; |
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56 |
/* |
while ((ch = cpu->machine->statistics_fields[i]) != '\0') { |
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* TODO: Everything below this line should be cleaned up :-) |
if (i != 0) |
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*/ |
strlcat(buf, " ", sizeof(buf)); |
59 |
a &= 0x03ffffff; |
|
60 |
{ |
switch (ch) { |
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static long long *array = NULL; |
case 'i': |
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static char *array_16kpage_in_use = NULL; |
snprintf(buf + strlen(buf), sizeof(buf), |
63 |
static int n = 0; |
"%p", (void *)ic->f); |
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a >>= DYNTRANS_INSTR_ALIGNMENT_SHIFT; |
break; |
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if (array == NULL) |
case 'p': |
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array = zeroed_alloc(sizeof(long long) * 16384*1024); |
/* Physical program counter address: */ |
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if (array_16kpage_in_use == NULL) |
/* (low_pc must be within the page!) */ |
68 |
array_16kpage_in_use = zeroed_alloc(sizeof(char) * 1024); |
if (low_pc < 0 || |
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a &= (16384*1024-1); |
low_pc >= DYNTRANS_IC_ENTRIES_PER_PAGE) |
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array[a] ++; |
strlcat(buf, "-", sizeof(buf)); |
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array_16kpage_in_use[a / 16384] = 1; |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
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n++; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
73 |
if ((n & 0x3fffffff) == 0) { |
a = cpu->cd.DYNTRANS_ARCH.cur_physpage->physaddr; |
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FILE *f = fopen("statistics.out", "w"); |
a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
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int i, j; |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
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printf("Saving statistics... "); fflush(stdout); |
a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT; |
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for (i=0; i<1024; i++) |
if (cpu->is_32bit) |
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if (array_16kpage_in_use[i]) { |
snprintf(buf + strlen(buf), sizeof(buf), |
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for (j=0; j<16384; j++) |
"0x%016"PRIx32, (uint32_t)a); |
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if (array[i*16384 + j] > 0) |
else |
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fprintf(f, "%lli\t0x%016llx\n", |
snprintf(buf + strlen(buf), sizeof(buf), |
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(long long)array[i*16384+j], |
"0x%016"PRIx64, (uint64_t)a); |
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(long long)((i*16384+j) << |
break; |
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DYNTRANS_INSTR_ALIGNMENT_SHIFT)); |
case 'v': |
85 |
} |
/* Virtual program counter address: */ |
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fclose(f); |
/* (low_pc inside the page, or in a delay slot) */ |
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printf("n=0x%08x\n", n); |
if (low_pc < 0 || |
88 |
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low_pc >= DYNTRANS_IC_ENTRIES_PER_PAGE + 2) |
89 |
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strlcat(buf, "-", sizeof(buf)); |
90 |
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a = cpu->pc; |
91 |
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a &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
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DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
93 |
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a += low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT; |
94 |
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if (cpu->is_32bit) |
95 |
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snprintf(buf + strlen(buf), sizeof(buf), |
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"0x%016"PRIx32, (uint32_t)a); |
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else |
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snprintf(buf + strlen(buf), sizeof(buf), |
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"0x%016"PRIx64, (uint64_t)a); |
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break; |
101 |
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} |
102 |
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i++; |
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} |
} |
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} |
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fprintf(cpu->machine->statistics_file, "%s\n", buf); |
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} |
} |
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#define S gather_statistics(cpu) |
#define S gather_statistics(cpu) |
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#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
113 |
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic; ic->f(cpu, ic); |
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic; \ |
114 |
#else |
cpu->cd.DYNTRANS_ARCH.next_ic += ic->arg[0]; \ |
115 |
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); |
ic->f(cpu, ic); |
116 |
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#else |
117 |
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118 |
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/* The normal instruction execution core: */ |
119 |
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#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); |
120 |
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121 |
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/* For heavy debugging: */ |
122 |
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/* #define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; \ |
123 |
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{ \ |
124 |
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int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \ |
125 |
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(size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \ |
126 |
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sizeof(struct DYNTRANS_IC); \ |
127 |
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printf("cur_ic_page=%p ic=%p (low_pc=0x%x)\n", \ |
128 |
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cpu->cd.DYNTRANS_ARCH.cur_ic_page, \ |
129 |
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ic, low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT); \ |
130 |
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} \ |
131 |
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ic->f(cpu, ic); */ |
132 |
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133 |
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/* static long long nr_of_I_calls = 0; */ |
134 |
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135 |
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/* Temporary hack for finding NULL bugs: */ |
136 |
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/* #define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; \ |
137 |
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nr_of_I_calls ++; \ |
138 |
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if (ic->f == NULL) { \ |
139 |
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int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \ |
140 |
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(size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \ |
141 |
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sizeof(struct DYNTRANS_IC); \ |
142 |
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cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << \ |
143 |
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DYNTRANS_INSTR_ALIGNMENT_SHIFT); \ |
144 |
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cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);\ |
145 |
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printf("Crash at %016"PRIx64"\n", cpu->pc); \ |
146 |
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printf("nr of I calls: %lli\n", nr_of_I_calls); \ |
147 |
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printf("Next ic = %p\n", cpu->cd. \ |
148 |
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DYNTRANS_ARCH.next_ic); \ |
149 |
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printf("cur ic page = %p\n", cpu->cd. \ |
150 |
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DYNTRANS_ARCH.cur_ic_page); \ |
151 |
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cpu->running = 0; \ |
152 |
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return 0; \ |
153 |
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} \ |
154 |
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ic->f(cpu, ic); */ |
155 |
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156 |
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/* Temporary hack for MIPS, to hunt for 32-bit/64-bit sign-extension bugs: */ |
157 |
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/* #define I { int k; for (k=1; k<=31; k++) \ |
158 |
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cpu->cd.mips.gpr[k] = (int32_t)cpu->cd.mips.gpr[k];\ |
159 |
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if (cpu->cd.mips.gpr[0] != 0) { \ |
160 |
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fatal("NOOOOOO\n"); exit(1); \ |
161 |
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} \ |
162 |
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ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); } |
163 |
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*/ |
164 |
#endif |
#endif |
165 |
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#endif /* STATIC STUFF */ |
166 |
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167 |
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168 |
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169 |
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#ifdef DYNTRANS_RUN_INSTR |
170 |
/* |
/* |
171 |
* XXX_cpu_run_instr(): |
* XXX_run_instr(): |
172 |
* |
* |
173 |
* Execute one or more instructions on a specific CPU, using dyntrans. |
* Execute one or more instructions on a specific CPU, using dyntrans. |
174 |
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* (For dualmode archs, this function is included twice.) |
175 |
* |
* |
176 |
* Return value is the number of instructions executed during this call, |
* Return value is the number of instructions executed during this call, |
177 |
* 0 if no instructions were executed. |
* 0 if no instructions were executed. |
178 |
*/ |
*/ |
179 |
int DYNTRANS_CPU_RUN_INSTR(struct emul *emul, struct cpu *cpu) |
int DYNTRANS_RUN_INSTR(struct cpu *cpu) |
180 |
{ |
{ |
181 |
#ifdef MODE32 |
MODE_uint_t cached_pc; |
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uint32_t cached_pc; |
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#else |
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uint64_t cached_pc; |
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#endif |
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182 |
int low_pc, n_instrs; |
int low_pc, n_instrs; |
183 |
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184 |
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/* Ugly... fix this some day. */ |
185 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
186 |
if (cpu->is_32bit) |
#ifdef MODE32 |
187 |
DYNTRANS_PC_TO_POINTERS32(cpu); |
DYNTRANS_PC_TO_POINTERS32(cpu); |
188 |
else |
#else |
189 |
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DYNTRANS_PC_TO_POINTERS(cpu); |
190 |
#endif |
#endif |
191 |
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#else |
192 |
DYNTRANS_PC_TO_POINTERS(cpu); |
DYNTRANS_PC_TO_POINTERS(cpu); |
193 |
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#endif |
194 |
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195 |
/* |
/* |
196 |
* Interrupt assertion? (This is _below_ the initial PC to pointer |
* Interrupt assertion? (This is _below_ the initial PC to pointer |
197 |
* conversion; if the conversion caused an exception of some kind |
* conversion; if the conversion caused an exception of some kind |
198 |
* then interrupts are probably disabled, and the exception will get |
* then interrupts are probably disabled, and the exception will get |
199 |
* priority over device interrupts.) |
* priority over device interrupts.) |
200 |
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* |
201 |
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* TODO: Turn this into a family-specific function somewhere... |
202 |
*/ |
*/ |
203 |
#ifdef DYNTRANS_ARM |
#ifdef DYNTRANS_ARM |
204 |
if (cpu->cd.arm.irq_asserted && !(cpu->cd.arm.cpsr & ARM_FLAG_I)) |
if (cpu->cd.arm.irq_asserted && !(cpu->cd.arm.cpsr & ARM_FLAG_I)) |
205 |
arm_exception(cpu, ARM_EXCEPTION_IRQ); |
arm_exception(cpu, ARM_EXCEPTION_IRQ); |
206 |
#endif |
#endif |
207 |
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#ifdef DYNTRANS_MIPS |
208 |
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{ |
209 |
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int enabled, mask; |
210 |
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int status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS]; |
211 |
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if (cpu->cd.mips.cpu_type.exc_model == EXC3K) { |
212 |
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/* R3000: */ |
213 |
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enabled = status & MIPS_SR_INT_IE; |
214 |
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} else { |
215 |
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/* R4000 and others: */ |
216 |
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enabled = (status & STATUS_IE) |
217 |
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&& !(status & STATUS_EXL) && !(status & STATUS_ERL); |
218 |
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/* Special case for R5900/C790/TX79: */ |
219 |
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if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 && |
220 |
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!(status & R5900_STATUS_EIE)) |
221 |
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enabled = 0; |
222 |
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} |
223 |
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mask = status & cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |
224 |
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& STATUS_IM_MASK; |
225 |
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226 |
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if (enabled && mask) |
227 |
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mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0, 0, 0, 0,0); |
228 |
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} |
229 |
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#endif |
230 |
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#ifdef DYNTRANS_PPC |
231 |
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if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) { |
232 |
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if (!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) |
233 |
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ppc_exception(cpu, PPC_EXCEPTION_DEC); |
234 |
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cpu->cd.ppc.dec_intr_pending = 0; |
235 |
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} |
236 |
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if (cpu->cd.ppc.irq_asserted && cpu->cd.ppc.msr & PPC_MSR_EE) |
237 |
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ppc_exception(cpu, PPC_EXCEPTION_EI); |
238 |
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#endif |
239 |
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#ifdef DYNTRANS_SH |
240 |
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if (cpu->cd.sh.int_to_assert > 0 && !(cpu->cd.sh.sr & SH_SR_BL) |
241 |
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&& ((cpu->cd.sh.sr & SH_SR_IMASK) >> SH_SR_IMASK_SHIFT) |
242 |
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< cpu->cd.sh.int_level) |
243 |
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sh_exception(cpu, 0, cpu->cd.sh.int_to_assert, 0); |
244 |
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#endif |
245 |
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246 |
cached_pc = cpu->pc; |
cached_pc = cpu->pc; |
247 |
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248 |
cpu->n_translated_instrs = 0; |
cpu->n_translated_instrs = 0; |
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cpu->running_translated = 1; |
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249 |
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250 |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
251 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
252 |
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|
253 |
if (single_step || cpu->machine->instruction_trace) { |
if (single_step || cpu->machine->instruction_trace |
254 |
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|| cpu->machine->register_dump) { |
255 |
/* |
/* |
256 |
* Single-step: |
* Single-step: |
257 |
*/ |
*/ |
258 |
struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic |
struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic; |
259 |
#ifndef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
if (cpu->machine->register_dump) { |
260 |
++ |
debug("\n"); |
261 |
#endif |
cpu_register_dump(cpu->machine, cpu, 1, 0x1); |
262 |
; |
} |
263 |
if (cpu->machine->instruction_trace) { |
if (cpu->machine->instruction_trace) { |
264 |
#ifdef DYNTRANS_X86 |
/* TODO/Note: This must be large enough to hold |
265 |
unsigned char instr[17]; |
any instruction for any ISA: */ |
266 |
cpu->cd.x86.cursegment = X86_S_CS; |
unsigned char instr[1 << |
267 |
cpu->cd.x86.seg_override = 0; |
DYNTRANS_INSTR_ALIGNMENT_SHIFT]; |
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#else |
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#ifdef DYNTRANS_M68K |
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unsigned char instr[16]; /* TODO: 16? */ |
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#else |
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unsigned char instr[4]; /* General case... */ |
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#endif |
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#endif |
|
268 |
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
269 |
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
270 |
fatal("XXX_cpu_run_instr(): could not read " |
fatal("XXX_run_instr(): could not read " |
271 |
"the instruction\n"); |
"the instruction\n"); |
272 |
} else |
} else { |
273 |
cpu_disassemble_instr(cpu->machine, cpu, |
#ifdef DYNTRANS_DELAYSLOT |
274 |
instr, 1, 0, 0); |
int len = |
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} |
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/* When single-stepping, multiple instruction calls cannot |
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be combined into one. This clears all translations: */ |
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if (cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & COMBINATIONS) { |
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int i; |
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for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) |
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cpu->cd.DYNTRANS_ARCH.cur_physpage->ics[i].f = |
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#ifdef DYNTRANS_DUALMODE_32 |
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cpu->is_32bit? |
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instr32(to_be_translated) : |
|
275 |
#endif |
#endif |
276 |
instr(to_be_translated); |
cpu_disassemble_instr( |
277 |
fatal("[ Note: The translation of physical page 0x%llx" |
cpu->machine, cpu, instr, 1, 0); |
278 |
" contained combinations of instructions; these " |
#ifdef DYNTRANS_DELAYSLOT |
279 |
"are now flushed because we are single-stepping." |
/* Show the instruction in the delay slot, |
280 |
" ]\n", (long long)cpu->cd.DYNTRANS_ARCH. |
if any: */ |
281 |
cur_physpage->physaddr); |
if (cpu->instruction_has_delayslot == NULL) |
282 |
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags &= |
fatal("WARNING: ihd func not yet" |
283 |
~(COMBINATIONS | TRANSLATIONS); |
" implemented?\n"); |
284 |
|
else if (cpu->instruction_has_delayslot(cpu, |
285 |
|
instr)) { |
286 |
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int saved_delayslot = cpu->delay_slot; |
287 |
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cpu->memory_rw(cpu, cpu->mem, cached_pc |
288 |
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+ len, &instr[0], |
289 |
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sizeof(instr), MEM_READ, |
290 |
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CACHE_INSTRUCTION); |
291 |
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cpu->delay_slot = DELAYED; |
292 |
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cpu->pc += len; |
293 |
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cpu_disassemble_instr(cpu->machine, |
294 |
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cpu, instr, 1, 0); |
295 |
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cpu->delay_slot = saved_delayslot; |
296 |
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cpu->pc -= len; |
297 |
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} |
298 |
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#endif |
299 |
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} |
300 |
} |
} |
301 |
|
|
302 |
if (show_opcode_statistics) |
if (cpu->machine->statistics_enabled) |
303 |
S; |
S; |
304 |
|
|
305 |
/* Execute just one instruction: */ |
/* Execute just one instruction: */ |
306 |
ic->f(cpu, ic); |
I; |
307 |
|
|
308 |
n_instrs = 1; |
n_instrs = 1; |
309 |
} else if (show_opcode_statistics) { |
} else if (cpu->machine->cycle_accurate) { |
310 |
|
/* Executing multiple instructions, and call devices' |
311 |
|
tick functions: */ |
312 |
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n_instrs = 0; |
313 |
|
for (;;) { |
314 |
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struct DYNTRANS_IC *ic; |
315 |
|
/* TODO: continue here */ |
316 |
|
int64_t cycles = cpu->cd.avr.extra_cycles; |
317 |
|
I; |
318 |
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n_instrs += 1; |
319 |
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cycles = cpu->cd.avr.extra_cycles - cycles + 1; |
320 |
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/* The instruction took 'cycles' cycles. */ |
321 |
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/* printf("A\n"); */ |
322 |
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while (cycles-- > 0) |
323 |
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cpu->machine->tick_func[1](cpu, cpu->machine->tick_extra[1]); |
324 |
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/* printf("B\n"); */ |
325 |
|
|
326 |
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if (n_instrs + cpu->n_translated_instrs >= |
327 |
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N_SAFE_DYNTRANS_LIMIT) |
328 |
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break; |
329 |
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} |
330 |
|
} else if (cpu->machine->statistics_enabled) { |
331 |
/* Gather statistics while executing multiple instructions: */ |
/* Gather statistics while executing multiple instructions: */ |
332 |
n_instrs = 0; |
n_instrs = 0; |
333 |
for (;;) { |
for (;;) { |
340 |
|
|
341 |
n_instrs += 24; |
n_instrs += 24; |
342 |
|
|
343 |
if (!cpu->running_translated || |
if (n_instrs + cpu->n_translated_instrs >= |
344 |
n_instrs + cpu->n_translated_instrs >= 16384) |
N_SAFE_DYNTRANS_LIMIT) |
345 |
break; |
break; |
346 |
} |
} |
347 |
} else { |
} else { |
358 |
|
|
359 |
I; I; I; I; I; I; I; I; I; I; |
I; I; I; I; I; I; I; I; I; I; |
360 |
|
|
361 |
n_instrs += 60; |
I; I; I; I; I; I; I; I; I; I; |
362 |
|
I; I; I; I; I; I; I; I; I; I; |
363 |
|
I; I; I; I; I; I; I; I; I; I; |
364 |
|
I; I; I; I; I; I; I; I; I; I; |
365 |
|
I; I; I; I; I; I; I; I; I; I; |
366 |
|
|
367 |
|
I; I; I; I; I; I; I; I; I; I; |
368 |
|
|
369 |
if (!cpu->running_translated || |
cpu->n_translated_instrs += 120; |
370 |
n_instrs + cpu->n_translated_instrs >= 16384) |
if (cpu->n_translated_instrs >= N_SAFE_DYNTRANS_LIMIT) |
371 |
break; |
break; |
372 |
} |
} |
373 |
} |
} |
374 |
|
|
375 |
|
n_instrs += cpu->n_translated_instrs; |
376 |
|
|
377 |
/* |
/* Synchronize the program counter: */ |
|
* Update the program counter and return the correct number of |
|
|
* executed instructions: |
|
|
*/ |
|
378 |
low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t) |
low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - (size_t) |
379 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC); |
cpu->cd.DYNTRANS_ARCH.cur_ic_page) / sizeof(struct DYNTRANS_IC); |
|
|
|
380 |
if (low_pc >= 0 && low_pc < DYNTRANS_IC_ENTRIES_PER_PAGE) { |
if (low_pc >= 0 && low_pc < DYNTRANS_IC_ENTRIES_PER_PAGE) { |
|
#ifdef DYNTRANS_ARM |
|
|
cpu->cd.arm.r[ARM_PC] &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1)<<2); |
|
|
cpu->cd.arm.r[ARM_PC] += (low_pc << 2); |
|
|
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
|
|
#else |
|
381 |
cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
382 |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
383 |
cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
|
#endif |
|
384 |
} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE) { |
} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE) { |
385 |
/* Switch to next page: */ |
/* Switch to next page: */ |
|
#ifdef DYNTRANS_ARM |
|
|
cpu->cd.arm.r[ARM_PC] &= ~((ARM_IC_ENTRIES_PER_PAGE-1) << 2); |
|
|
cpu->cd.arm.r[ARM_PC] += (ARM_IC_ENTRIES_PER_PAGE << 2); |
|
|
cpu->pc = cpu->cd.arm.r[ARM_PC]; |
|
|
#else |
|
386 |
cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
387 |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
388 |
cpu->pc += (DYNTRANS_IC_ENTRIES_PER_PAGE << |
cpu->pc += (DYNTRANS_IC_ENTRIES_PER_PAGE << |
389 |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
390 |
|
} else if (low_pc == DYNTRANS_IC_ENTRIES_PER_PAGE + 1) { |
391 |
|
/* Switch to next page and skip an instruction which was |
392 |
|
already executed (in a delay slot): */ |
393 |
|
cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << |
394 |
|
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
395 |
|
cpu->pc += ((DYNTRANS_IC_ENTRIES_PER_PAGE + 1) << |
396 |
|
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
397 |
|
} |
398 |
|
|
399 |
|
#ifdef DYNTRANS_MIPS |
400 |
|
/* Update the count register (on everything except EXC3K): */ |
401 |
|
if (cpu->cd.mips.cpu_type.exc_model != EXC3K) { |
402 |
|
uint32_t old = cpu->cd.mips.coproc[0]->reg[COP0_COUNT]; |
403 |
|
int32_t diff1 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - old; |
404 |
|
int32_t diff2; |
405 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COUNT] = |
406 |
|
(int32_t) (old + n_instrs); |
407 |
|
diff2 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - |
408 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COUNT]; |
409 |
|
|
410 |
|
if (cpu->cd.mips.compare_register_set) { |
411 |
|
#if 1 |
412 |
|
/* Not yet. TODO */ |
413 |
|
if (cpu->machine->emulated_hz > 0) { |
414 |
|
if (cpu->cd.mips.compare_interrupts_pending > 0) |
415 |
|
INTERRUPT_ASSERT( |
416 |
|
cpu->cd.mips.irq_compare); |
417 |
|
} else |
418 |
#endif |
#endif |
419 |
} else { |
{ |
420 |
/* debug("debug: Outside a page (This is actually ok)\n"); */ |
if (diff1 > 0 && diff2 <= 0) |
421 |
|
INTERRUPT_ASSERT( |
422 |
|
cpu->cd.mips.irq_compare); |
423 |
|
} |
424 |
|
} |
425 |
} |
} |
426 |
|
#endif |
427 |
|
#ifdef DYNTRANS_PPC |
428 |
|
/* Update the Decrementer and Time base registers: */ |
429 |
|
{ |
430 |
|
uint32_t old = cpu->cd.ppc.spr[SPR_DEC]; |
431 |
|
cpu->cd.ppc.spr[SPR_DEC] = (uint32_t) (old - n_instrs); |
432 |
|
if ((old >> 31) == 0 && (cpu->cd.ppc.spr[SPR_DEC] >> 31) == 1 |
433 |
|
&& !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) |
434 |
|
cpu->cd.ppc.dec_intr_pending = 1; |
435 |
|
old = cpu->cd.ppc.spr[SPR_TBL]; |
436 |
|
cpu->cd.ppc.spr[SPR_TBL] += n_instrs; |
437 |
|
if ((old >> 31) == 1 && (cpu->cd.ppc.spr[SPR_TBL] >> 31) == 0) |
438 |
|
cpu->cd.ppc.spr[SPR_TBU] ++; |
439 |
|
} |
440 |
|
#endif |
441 |
|
|
442 |
return n_instrs + cpu->n_translated_instrs; |
/* Return the nr of instructions executed: */ |
443 |
|
return n_instrs; |
444 |
} |
} |
445 |
#endif /* DYNTRANS_CPU_RUN_INSTR */ |
#endif /* DYNTRANS_RUN_INSTR */ |
446 |
|
|
447 |
|
|
448 |
|
|
460 |
char *symbol; |
char *symbol; |
461 |
uint64_t ot; |
uint64_t ot; |
462 |
int x, print_dots = 1, n_args_to_print = |
int x, print_dots = 1, n_args_to_print = |
463 |
#ifdef DYNTRANS_ALPHA |
#if defined(DYNTRANS_ALPHA) || defined(DYNTRANS_SPARC) |
464 |
6 |
6 |
465 |
#else |
#else |
466 |
#ifdef DYNTRANS_SH |
#if defined(DYNTRANS_SH) || defined(DYNTRANS_M88K) |
467 |
8 |
8 /* Both for 32-bit and 64-bit SuperH, and M88K */ |
468 |
#else |
#else |
469 |
4 /* Default value for most archs */ |
4 /* Default value for most archs */ |
470 |
#endif |
#endif |
488 |
* than were passed in register. |
* than were passed in register. |
489 |
*/ |
*/ |
490 |
for (x=0; x<n_args_to_print; x++) { |
for (x=0; x<n_args_to_print; x++) { |
491 |
int64_t d; |
int64_t d = cpu->cd.DYNTRANS_ARCH. |
|
#ifdef DYNTRANS_X86 |
|
|
d = 0; /* TODO */ |
|
|
#else |
|
|
/* Args in registers: */ |
|
|
d = cpu->cd.DYNTRANS_ARCH. |
|
492 |
#ifdef DYNTRANS_ALPHA |
#ifdef DYNTRANS_ALPHA |
493 |
r[ALPHA_A0 |
r[ALPHA_A0 |
494 |
#endif |
#endif |
500 |
they go downwards, ie. 22,23 and so on */ |
they go downwards, ie. 22,23 and so on */ |
501 |
r[24 |
r[24 |
502 |
#endif |
#endif |
|
#ifdef DYNTRANS_HPPA |
|
|
r[0 /* TODO */ |
|
|
#endif |
|
|
#ifdef DYNTRANS_I960 |
|
|
r[0 /* TODO */ |
|
|
#endif |
|
|
#ifdef DYNTRANS_IA64 |
|
|
r[0 /* TODO */ |
|
|
#endif |
|
|
#ifdef DYNTRANS_M68K |
|
|
d[0 /* TODO */ |
|
|
#endif |
|
503 |
#ifdef DYNTRANS_MIPS |
#ifdef DYNTRANS_MIPS |
504 |
gpr[MIPS_GPR_A0 |
gpr[MIPS_GPR_A0 |
505 |
#endif |
#endif |
506 |
|
#ifdef DYNTRANS_M88K |
507 |
|
r[2 /* r2..r9 */ |
508 |
|
#endif |
509 |
#ifdef DYNTRANS_PPC |
#ifdef DYNTRANS_PPC |
510 |
gpr[3 |
gpr[3 |
511 |
#endif |
#endif |
512 |
#ifdef DYNTRANS_SH |
#ifdef DYNTRANS_SH |
513 |
r[2 |
r[4 /* NetBSD seems to use 4? But 2 seems |
514 |
|
to be used by other code? TODO */ |
515 |
#endif |
#endif |
516 |
#ifdef DYNTRANS_SPARC |
#ifdef DYNTRANS_SPARC |
517 |
r_i[0 |
r[8 /* o0..o5 */ |
518 |
#endif |
#endif |
519 |
+ x]; |
+ x]; |
520 |
#endif |
|
521 |
symbol = get_symbol_name(&cpu->machine->symbol_context, d, &ot); |
symbol = get_symbol_name(&cpu->machine->symbol_context, d, &ot); |
522 |
|
|
523 |
if (d > -256 && d < 256) |
if (d > -256 && d < 256) |
529 |
fatal("&%s", symbol); |
fatal("&%s", symbol); |
530 |
else { |
else { |
531 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
532 |
fatal("0x%x", (int)d); |
fatal("0x%"PRIx32, (uint32_t)d); |
533 |
else |
else |
534 |
fatal("0x%llx", (long long)d); |
fatal("0x%"PRIx64, (uint64_t)d); |
535 |
} |
} |
536 |
|
|
537 |
if (x < n_args_to_print - 1) |
if (x < n_args_to_print - 1) |
546 |
|
|
547 |
|
|
548 |
#ifdef DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE |
#ifdef DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE |
|
/* forward declaration of to_be_translated and end_of_page: */ |
|
|
static void instr(to_be_translated)(struct cpu *, struct DYNTRANS_IC *); |
|
|
static void instr(end_of_page)(struct cpu *,struct DYNTRANS_IC *); |
|
|
#ifdef DYNTRANS_DUALMODE_32 |
|
|
static void instr32(to_be_translated)(struct cpu *, struct DYNTRANS_IC *); |
|
|
static void instr32(end_of_page)(struct cpu *,struct DYNTRANS_IC *); |
|
|
#endif |
|
549 |
/* |
/* |
550 |
* XXX_tc_allocate_default_page(): |
* XXX_tc_allocate_default_page(): |
551 |
* |
* |
556 |
uint64_t physaddr) |
uint64_t physaddr) |
557 |
{ |
{ |
558 |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
|
int i; |
|
559 |
|
|
|
/* Create the physpage header: */ |
|
560 |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
561 |
+ cpu->translation_cache_cur_ofs); |
+ cpu->translation_cache_cur_ofs); |
|
ppp->next_ofs = 0; |
|
|
ppp->physaddr = physaddr; |
|
562 |
|
|
563 |
/* TODO: Is this faster than copying an entire template page? */ |
/* Copy the entire template page first: */ |
564 |
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) |
memcpy(ppp, cpu->cd.DYNTRANS_ARCH.physpage_template, sizeof( |
565 |
ppp->ics[i].f = |
struct DYNTRANS_TC_PHYSPAGE)); |
|
#ifdef DYNTRANS_DUALMODE_32 |
|
|
cpu->is_32bit? instr32(to_be_translated) : |
|
|
#endif |
|
|
instr(to_be_translated); |
|
566 |
|
|
567 |
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE].f = |
ppp->physaddr = physaddr & ~(DYNTRANS_PAGESIZE - 1); |
|
#ifdef DYNTRANS_DUALMODE_32 |
|
|
cpu->is_32bit? instr32(end_of_page) : |
|
|
#endif |
|
|
instr(end_of_page); |
|
568 |
|
|
569 |
cpu->translation_cache_cur_ofs += sizeof(struct DYNTRANS_TC_PHYSPAGE); |
cpu->translation_cache_cur_ofs += sizeof(struct DYNTRANS_TC_PHYSPAGE); |
570 |
|
|
571 |
cpu->translation_cache_cur_ofs --; |
cpu->translation_cache_cur_ofs --; |
572 |
cpu->translation_cache_cur_ofs |= 63; |
cpu->translation_cache_cur_ofs |= 127; |
573 |
cpu->translation_cache_cur_ofs ++; |
cpu->translation_cache_cur_ofs ++; |
574 |
} |
} |
575 |
#endif /* DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE */ |
#endif /* DYNTRANS_TC_ALLOCATE_DEFAULT_PAGE */ |
589 |
#else |
#else |
590 |
uint64_t |
uint64_t |
591 |
#endif |
#endif |
592 |
cached_pc, physaddr; |
cached_pc = cpu->pc, physaddr = 0; |
593 |
uint32_t physpage_ofs; |
uint32_t physpage_ofs; |
594 |
int ok, pagenr, table_index; |
int ok, pagenr, table_index; |
595 |
uint32_t *physpage_entryp; |
uint32_t *physpage_entryp; |
596 |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
597 |
|
|
598 |
#ifdef MODE32 |
#ifdef MODE32 |
599 |
int index; |
int index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
|
cached_pc = cpu->pc; |
|
|
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
|
600 |
#else |
#else |
601 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
602 |
uint32_t a, b; |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
603 |
int kernel = 0; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
604 |
struct alpha_vph_page *vph_p; |
uint32_t x1, x2, x3; |
605 |
cached_pc = cpu->pc; |
struct DYNTRANS_L2_64_TABLE *l2; |
606 |
a = (cached_pc >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
struct DYNTRANS_L3_64_TABLE *l3; |
607 |
b = (cached_pc >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
608 |
if ((cached_pc >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1; |
609 |
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
610 |
kernel = 1; |
x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3; |
611 |
} else |
/* fatal("X3: cached_pc=%016"PRIx64" x1=%x x2=%x x3=%x\n", |
612 |
vph_p = cpu->cd.alpha.vph_table0[a]; |
(uint64_t)cached_pc, (int)x1, (int)x2, (int)x3); */ |
613 |
#else |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
614 |
#ifdef DYNTRANS_IA64 |
/* fatal(" l2 = %p\n", l2); */ |
615 |
fatal("IA64 todo\n"); |
l3 = l2->l3[x2]; |
616 |
#else |
/* fatal(" l3 = %p\n", l3); */ |
|
fatal("Neither alpha, ia64, nor 32-bit? 3\n"); |
|
|
exit(1); |
|
|
#endif |
|
|
#endif |
|
617 |
#endif |
#endif |
618 |
|
|
619 |
/* Virtual to physical address translation: */ |
/* Virtual to physical address translation: */ |
624 |
ok = 1; |
ok = 1; |
625 |
} |
} |
626 |
#else |
#else |
627 |
#ifdef DYNTRANS_ALPHA |
if (l3->host_load[x3] != NULL) { |
628 |
if (vph_p->host_load[b] != NULL) { |
physaddr = l3->phys_addr[x3]; |
|
physaddr = vph_p->phys_addr[b]; |
|
629 |
ok = 1; |
ok = 1; |
630 |
} |
} |
|
#else |
|
|
#ifdef DYNTRANS_IA64 |
|
|
fatal("IA64 todo\n"); |
|
|
#else |
|
|
fatal("Neither alpha, ia64, nor 32-bit? 4\n"); |
|
|
exit(1); |
|
|
#endif |
|
|
#endif |
|
631 |
#endif |
#endif |
632 |
|
|
633 |
if (!ok) { |
if (!ok) { |
634 |
uint64_t paddr; |
uint64_t paddr; |
635 |
if (cpu->translate_address != NULL) |
if (cpu->translate_v2p != NULL) { |
636 |
ok = cpu->translate_address(cpu, cached_pc, |
uint64_t vaddr = |
637 |
&paddr, FLAG_INSTR); |
#if defined(MODE32) && defined(DYNTRANS_MIPS) |
638 |
else { |
/* 32-bit MIPS is _sign_ extend, not zero. */ |
639 |
|
(int32_t) |
640 |
|
#endif |
641 |
|
cached_pc; |
642 |
|
ok = cpu->translate_v2p( |
643 |
|
cpu, vaddr, &paddr, FLAG_INSTR); |
644 |
|
} else { |
645 |
paddr = cached_pc; |
paddr = cached_pc; |
646 |
ok = 1; |
ok = 1; |
647 |
} |
} |
648 |
if (!ok) { |
if (!ok) { |
649 |
/* |
/* |
650 |
fatal("TODO: instruction vaddr=>paddr translation" |
* The PC is now set to the exception handler. |
651 |
" failed. vaddr=0x%llx\n", (long long)cached_pc); |
* Try to find the paddr in the translation arrays, |
652 |
fatal("!! cpu->pc=0x%llx arm_pc=0x%x\n", (long long)cpu->pc, |
* or if that fails, call translate_v2p for the |
653 |
cpu->cd.arm.r[ARM_PC]); |
* exception handler. |
654 |
*/ |
*/ |
655 |
ok = cpu->translate_address(cpu, cpu->pc, &paddr, |
/* fatal("TODO: instruction vaddr=>paddr translation " |
656 |
FLAG_INSTR); |
"failed. vaddr=0x%"PRIx64"\n", (uint64_t)cached_pc); |
657 |
/* |
fatal("!! cpu->pc=0x%"PRIx64"\n", (uint64_t)cpu->pc); */ |
658 |
printf("EXCEPTION HANDLER: vaddr = 0x%x ==> paddr = 0x%x\n", |
|
659 |
(int)cpu->pc, (int)paddr); |
/* If there was an exception, the PC has changed. |
660 |
fatal("!? cpu->pc=0x%llx arm_pc=0x%x\n", (long long)cpu->pc, |
Update cached_pc: */ |
661 |
cpu->cd.arm.r[ARM_PC]); |
cached_pc = cpu->pc; |
662 |
*/ |
|
663 |
|
#ifdef MODE32 |
664 |
|
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
665 |
|
if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) { |
666 |
|
paddr = cpu->cd.DYNTRANS_ARCH.phys_addr[index]; |
667 |
|
ok = 1; |
668 |
|
} |
669 |
|
#else |
670 |
|
x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1; |
671 |
|
x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) |
672 |
|
& mask2; |
673 |
|
x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N |
674 |
|
- DYNTRANS_L3N)) & mask3; |
675 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
676 |
|
l3 = l2->l3[x2]; |
677 |
|
if (l3->host_load[x3] != NULL) { |
678 |
|
paddr = l3->phys_addr[x3]; |
679 |
|
ok = 1; |
680 |
|
} |
681 |
|
#endif |
682 |
|
|
683 |
|
if (!ok) { |
684 |
|
ok = cpu->translate_v2p(cpu, cpu->pc, &paddr, |
685 |
|
FLAG_INSTR); |
686 |
|
} |
687 |
|
|
688 |
|
/* printf("EXCEPTION HANDLER: vaddr = 0x%x ==> " |
689 |
|
"paddr = 0x%x\n", (int)cpu->pc, (int)paddr); |
690 |
|
fatal("!? cpu->pc=0x%"PRIx64"\n", (uint64_t)cpu->pc); */ |
691 |
|
|
692 |
if (!ok) { |
if (!ok) { |
693 |
fatal("FATAL: could not find physical" |
fatal("FATAL: could not find physical" |
694 |
" address of the exception handler?"); |
" address of the exception handler?"); |
695 |
exit(1); |
exit(1); |
696 |
} |
} |
697 |
} |
} |
698 |
cached_pc = cpu->pc; |
|
|
#ifdef MODE32 |
|
|
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
|
|
#endif |
|
699 |
physaddr = paddr; |
physaddr = paddr; |
700 |
} |
} |
701 |
|
|
702 |
|
physaddr &= ~(DYNTRANS_PAGESIZE - 1); |
703 |
|
|
704 |
#ifdef MODE32 |
#ifdef MODE32 |
705 |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] == NULL) { |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] == NULL) { |
706 |
|
#else |
707 |
|
if (l3->host_load[x3] == NULL) { |
708 |
|
#endif |
709 |
|
int q = DYNTRANS_PAGESIZE - 1; |
710 |
unsigned char *host_page = memory_paddr_to_hostaddr(cpu->mem, |
unsigned char *host_page = memory_paddr_to_hostaddr(cpu->mem, |
711 |
physaddr, MEM_READ); |
physaddr, MEM_READ); |
712 |
if (host_page != NULL) { |
if (host_page != NULL) { |
|
int q = DYNTRANS_PAGESIZE - 1; |
|
|
host_page += (physaddr & |
|
|
((1 << BITS_PER_MEMBLOCK) - 1) & ~q); |
|
713 |
cpu->update_translation_table(cpu, cached_pc & ~q, |
cpu->update_translation_table(cpu, cached_pc & ~q, |
714 |
host_page, TLB_CODE, physaddr & ~q); |
host_page, 0, physaddr); |
715 |
} |
} |
716 |
} |
} |
|
#endif |
|
717 |
|
|
718 |
if (cpu->translation_cache_cur_ofs >= DYNTRANS_CACHE_SIZE) { |
if (cpu->translation_cache_cur_ofs >= dyntrans_cache_size) { |
719 |
|
#ifdef UNSTABLE_DEVEL |
720 |
fatal("[ dyntrans: resetting the translation cache ]\n"); |
fatal("[ dyntrans: resetting the translation cache ]\n"); |
721 |
|
#endif |
722 |
cpu_create_or_reset_tc(cpu); |
cpu_create_or_reset_tc(cpu); |
723 |
} |
} |
724 |
|
|
733 |
while (physpage_ofs != 0) { |
while (physpage_ofs != 0) { |
734 |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
735 |
+ physpage_ofs); |
+ physpage_ofs); |
736 |
|
|
737 |
/* If we found the page in the cache, then we're done: */ |
/* If we found the page in the cache, then we're done: */ |
738 |
if (ppp->physaddr == physaddr) |
if (ppp->physaddr == physaddr) |
739 |
break; |
break; |
740 |
|
|
741 |
/* Try the next page in the chain: */ |
/* Try the next page in the chain: */ |
742 |
physpage_ofs = ppp->next_ofs; |
physpage_ofs = ppp->next_ofs; |
743 |
} |
} |
744 |
|
|
745 |
/* If the offset is 0 (or ppp is NULL), then we need to create a |
/* |
746 |
new "default" empty translation page. */ |
* If the offset is 0, then no translation exists yet for this |
747 |
|
* physical address. Let's create a new page, and add it first in |
748 |
|
* the chain. |
749 |
|
*/ |
750 |
|
if (physpage_ofs == 0) { |
751 |
|
uint32_t previous_first_page_in_chain; |
752 |
|
|
753 |
if (ppp == NULL) { |
/* fatal("CREATING page %lli (physaddr 0x%"PRIx64"), table " |
754 |
/* fatal("CREATING page %lli (physaddr 0x%llx), table index " |
"index %i\n", (long long)pagenr, (uint64_t)physaddr, |
|
"%i\n", (long long)pagenr, (long long)physaddr, |
|
755 |
(int)table_index); */ |
(int)table_index); */ |
756 |
|
|
757 |
|
previous_first_page_in_chain = *physpage_entryp; |
758 |
|
|
759 |
|
/* Insert the new page first in the chain: */ |
760 |
*physpage_entryp = physpage_ofs = |
*physpage_entryp = physpage_ofs = |
761 |
cpu->translation_cache_cur_ofs; |
cpu->translation_cache_cur_ofs; |
762 |
|
|
765 |
|
|
766 |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
767 |
+ physpage_ofs); |
+ physpage_ofs); |
768 |
|
|
769 |
|
/* Point to the other pages in the same chain: */ |
770 |
|
ppp->next_ofs = previous_first_page_in_chain; |
771 |
} |
} |
772 |
|
|
773 |
|
/* Here, ppp points to a valid physical page struct. */ |
774 |
|
|
775 |
#ifdef MODE32 |
#ifdef MODE32 |
776 |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) |
777 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = ppp; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = ppp; |
778 |
|
#else |
779 |
|
if (l3->host_load[x3] != NULL) |
780 |
|
l3->phys_page[x3] = ppp; |
781 |
#endif |
#endif |
782 |
|
|
783 |
#ifdef DYNTRANS_ALPHA |
/* |
784 |
if (vph_p->host_load[b] != NULL) |
* If there are no translations yet on this page, then mark it |
785 |
vph_p->phys_page[b] = ppp; |
* as non-writable. If there are already translations, then it |
786 |
#endif |
* should already have been marked as non-writable. |
787 |
|
*/ |
788 |
cpu->invalidate_translation_caches(cpu, physaddr, |
if (ppp->translations == 0) { |
789 |
JUST_MARK_AS_NON_WRITABLE | INVALIDATE_PADDR); |
cpu->invalidate_translation_caches(cpu, physaddr, |
790 |
|
JUST_MARK_AS_NON_WRITABLE | INVALIDATE_PADDR); |
791 |
|
} |
792 |
|
|
|
/* cpu->cd.DYNTRANS_ARCH.cur_physpage = ppp; */ |
|
793 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0]; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0]; |
794 |
|
|
795 |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
796 |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
797 |
|
|
798 |
/* printf("cached_pc=0x%016llx pagenr=%lli table_index=%lli, " |
/* printf("cached_pc=0x%016"PRIx64" pagenr=%lli table_index=%lli, " |
799 |
"physpage_ofs=0x%016llx\n", (long long)cached_pc, (long long)pagenr, |
"physpage_ofs=0x%016"PRIx64"\n", (uint64_t)cached_pc, (long long) |
800 |
(long long)table_index, (long long)physpage_ofs); */ |
pagenr, (long long)table_index, (uint64_t)physpage_ofs); */ |
801 |
} |
} |
802 |
|
|
803 |
|
|
821 |
#else |
#else |
822 |
uint64_t |
uint64_t |
823 |
#endif |
#endif |
824 |
cached_pc; |
cached_pc = cpu->pc; |
825 |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
826 |
|
|
827 |
#ifdef MODE32 |
#ifdef MODE32 |
828 |
int index; |
int index; |
|
cached_pc = cpu->pc; |
|
829 |
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
830 |
ppp = cpu->cd.DYNTRANS_ARCH.phys_page[index]; |
ppp = cpu->cd.DYNTRANS_ARCH.phys_page[index]; |
831 |
if (ppp != NULL) |
if (ppp != NULL) |
832 |
goto have_it; |
goto have_it; |
833 |
#else |
#else |
834 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
835 |
uint32_t a, b; |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
836 |
int kernel = 0; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
837 |
struct alpha_vph_page *vph_p; |
uint32_t x1, x2, x3; |
838 |
cached_pc = cpu->pc; |
struct DYNTRANS_L2_64_TABLE *l2; |
839 |
a = (cached_pc >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
struct DYNTRANS_L3_64_TABLE *l3; |
840 |
b = (cached_pc >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
841 |
if ((cached_pc >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1; |
842 |
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
843 |
kernel = 1; |
x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3; |
844 |
} else |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
845 |
vph_p = cpu->cd.alpha.vph_table0[a]; |
l3 = l2->l3[x2]; |
846 |
if (vph_p != cpu->cd.alpha.vph_default_page) { |
ppp = l3->phys_page[x3]; |
847 |
ppp = vph_p->phys_page[b]; |
if (ppp != NULL) |
848 |
if (ppp != NULL) |
goto have_it; |
|
goto have_it; |
|
|
} |
|
|
#else |
|
|
#ifdef DYNTRANS_IA64 |
|
|
fatal("IA64 todo\n"); |
|
|
#else |
|
|
fatal("Neither alpha, ia64, nor 32-bit? 1\n"); |
|
|
{ char *p = (char *) 0; *p = 0; } |
|
|
exit(1); |
|
|
#endif |
|
|
#endif |
|
849 |
#endif |
#endif |
850 |
|
|
851 |
DYNTRANS_PC_TO_POINTERS_GENERIC(cpu); |
DYNTRANS_PC_TO_POINTERS_GENERIC(cpu); |
853 |
|
|
854 |
/* Quick return path: */ |
/* Quick return path: */ |
855 |
have_it: |
have_it: |
|
/* cpu->cd.DYNTRANS_ARCH.cur_physpage = ppp; */ |
|
856 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0]; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0]; |
857 |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
858 |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
859 |
|
|
860 |
/* printf("cached_pc=0x%016llx pagenr=%lli table_index=%lli, " |
/* printf("cached_pc=0x%016"PRIx64" pagenr=%lli table_index=%lli, " |
861 |
"physpage_ofs=0x%016llx\n", (long long)cached_pc, (long long)pagenr, |
"physpage_ofs=0x%016"PRIx64"\n", (uint64_t)cached_pc, (long long) |
862 |
(long long)table_index, (long long)physpage_ofs); */ |
pagenr, (long long)table_index, (uint64_t)physpage_ofs); */ |
863 |
} |
} |
864 |
#endif /* DYNTRANS_PC_TO_POINTERS_FUNC */ |
#endif /* DYNTRANS_PC_TO_POINTERS_FUNC */ |
865 |
|
|
866 |
|
|
867 |
|
|
868 |
|
#ifdef DYNTRANS_INIT_TABLES |
869 |
|
|
870 |
|
/* forward declaration of to_be_translated and end_of_page: */ |
871 |
|
static void instr(to_be_translated)(struct cpu *, struct DYNTRANS_IC *); |
872 |
|
static void instr(end_of_page)(struct cpu *,struct DYNTRANS_IC *); |
873 |
|
#ifdef DYNTRANS_DUALMODE_32 |
874 |
|
static void instr32(to_be_translated)(struct cpu *, struct DYNTRANS_IC *); |
875 |
|
static void instr32(end_of_page)(struct cpu *,struct DYNTRANS_IC *); |
876 |
|
#endif |
877 |
|
|
878 |
|
#ifdef DYNTRANS_DELAYSLOT |
879 |
|
static void instr(end_of_page2)(struct cpu *,struct DYNTRANS_IC *); |
880 |
|
#ifdef DYNTRANS_DUALMODE_32 |
881 |
|
static void instr32(end_of_page2)(struct cpu *,struct DYNTRANS_IC *); |
882 |
|
#endif |
883 |
|
#endif |
884 |
|
|
885 |
|
/* |
886 |
|
* XXX_init_tables(): |
887 |
|
* |
888 |
|
* Initializes the default translation page (for newly allocated pages), and |
889 |
|
* for 64-bit emulation it also initializes 64-bit dummy tables and pointers. |
890 |
|
*/ |
891 |
|
void DYNTRANS_INIT_TABLES(struct cpu *cpu) |
892 |
|
{ |
893 |
|
#ifndef MODE32 |
894 |
|
struct DYNTRANS_L2_64_TABLE *dummy_l2; |
895 |
|
struct DYNTRANS_L3_64_TABLE *dummy_l3; |
896 |
|
int x1, x2; |
897 |
|
#endif |
898 |
|
int i; |
899 |
|
struct DYNTRANS_TC_PHYSPAGE *ppp = malloc(sizeof( |
900 |
|
struct DYNTRANS_TC_PHYSPAGE)); |
901 |
|
|
902 |
|
if (ppp == NULL) { |
903 |
|
fprintf(stderr, "out of memory\n"); |
904 |
|
exit(1); |
905 |
|
} |
906 |
|
|
907 |
|
ppp->next_ofs = 0; |
908 |
|
ppp->translations = 0; |
909 |
|
/* ppp->physaddr is filled in by the page allocator */ |
910 |
|
|
911 |
|
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) { |
912 |
|
ppp->ics[i].f = |
913 |
|
#ifdef DYNTRANS_DUALMODE_32 |
914 |
|
cpu->is_32bit? instr32(to_be_translated) : |
915 |
|
#endif |
916 |
|
instr(to_be_translated); |
917 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
918 |
|
ppp->ics[i].arg[0] = 0; |
919 |
|
#endif |
920 |
|
} |
921 |
|
|
922 |
|
/* End-of-page: */ |
923 |
|
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].f = |
924 |
|
#ifdef DYNTRANS_DUALMODE_32 |
925 |
|
cpu->is_32bit? instr32(end_of_page) : |
926 |
|
#endif |
927 |
|
instr(end_of_page); |
928 |
|
|
929 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
930 |
|
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].arg[0] = 0; |
931 |
|
#endif |
932 |
|
|
933 |
|
/* End-of-page-2, for delay-slot architectures: */ |
934 |
|
#ifdef DYNTRANS_DELAYSLOT |
935 |
|
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 1].f = |
936 |
|
#ifdef DYNTRANS_DUALMODE_32 |
937 |
|
cpu->is_32bit? instr32(end_of_page2) : |
938 |
|
#endif |
939 |
|
instr(end_of_page2); |
940 |
|
#endif |
941 |
|
|
942 |
|
cpu->cd.DYNTRANS_ARCH.physpage_template = ppp; |
943 |
|
|
944 |
|
|
945 |
|
/* Prepare 64-bit virtual address translation tables: */ |
946 |
|
#ifndef MODE32 |
947 |
|
if (cpu->is_32bit) |
948 |
|
return; |
949 |
|
|
950 |
|
dummy_l2 = zeroed_alloc(sizeof(struct DYNTRANS_L2_64_TABLE)); |
951 |
|
dummy_l3 = zeroed_alloc(sizeof(struct DYNTRANS_L3_64_TABLE)); |
952 |
|
|
953 |
|
cpu->cd.DYNTRANS_ARCH.l2_64_dummy = dummy_l2; |
954 |
|
cpu->cd.DYNTRANS_ARCH.l3_64_dummy = dummy_l3; |
955 |
|
|
956 |
|
for (x1 = 0; x1 < (1 << DYNTRANS_L1N); x1 ++) |
957 |
|
cpu->cd.DYNTRANS_ARCH.l1_64[x1] = dummy_l2; |
958 |
|
|
959 |
|
for (x2 = 0; x2 < (1 << DYNTRANS_L2N); x2 ++) |
960 |
|
dummy_l2->l3[x2] = dummy_l3; |
961 |
|
#endif |
962 |
|
} |
963 |
|
#endif /* DYNTRANS_INIT_TABLES */ |
964 |
|
|
965 |
|
|
966 |
|
|
967 |
#ifdef DYNTRANS_INVAL_ENTRY |
#ifdef DYNTRANS_INVAL_ENTRY |
968 |
/* |
/* |
969 |
* XXX_invalidate_tlb_entry(): |
* XXX_invalidate_tlb_entry(): |
986 |
uint32_t index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
uint32_t index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
987 |
|
|
988 |
#ifdef DYNTRANS_ARM |
#ifdef DYNTRANS_ARM |
989 |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 3] &= ~(1 << (index & 7)); |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] &= ~(1 << (index & 31)); |
990 |
#endif |
#endif |
991 |
|
|
992 |
if (flags & JUST_MARK_AS_NON_WRITABLE) { |
if (flags & JUST_MARK_AS_NON_WRITABLE) { |
994 |
(int)vaddr_page); */ |
(int)vaddr_page); */ |
995 |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
996 |
} else { |
} else { |
997 |
|
int tlbi = cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index]; |
998 |
cpu->cd.DYNTRANS_ARCH.host_load[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_load[index] = NULL; |
999 |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
1000 |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = 0; |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = 0; |
1001 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
1002 |
|
if (tlbi > 0) |
1003 |
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[tlbi-1].valid = 0; |
1004 |
cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = 0; |
cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = 0; |
1005 |
} |
} |
1006 |
#else |
#else |
1007 |
/* 2-level: */ |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
1008 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
1009 |
struct alpha_vph_page *vph_p; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
1010 |
uint32_t a, b; |
uint32_t x1, x2, x3; |
1011 |
int kernel = 0; |
struct DYNTRANS_L2_64_TABLE *l2; |
1012 |
|
struct DYNTRANS_L3_64_TABLE *l3; |
1013 |
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
|
1014 |
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1015 |
if ((vaddr_page >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
1016 |
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))& mask3; |
|
kernel = 1; |
|
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
1017 |
|
|
1018 |
if (vph_p == cpu->cd.alpha.vph_default_page) { |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1019 |
fatal("alpha_invalidate_tlb_entry(): huh? Problem 1.\n"); |
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) |
1020 |
exit(1); |
return; |
1021 |
} |
|
1022 |
|
l3 = l2->l3[x2]; |
1023 |
|
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) |
1024 |
|
return; |
1025 |
|
|
1026 |
if (flags & JUST_MARK_AS_NON_WRITABLE) { |
if (flags & JUST_MARK_AS_NON_WRITABLE) { |
1027 |
vph_p->host_store[b] = NULL; |
l3->host_store[x3] = NULL; |
1028 |
return; |
return; |
1029 |
} |
} |
1030 |
vph_p->host_load[b] = NULL; |
|
1031 |
vph_p->host_store[b] = NULL; |
#ifdef BUGHUNT |
1032 |
vph_p->phys_addr[b] = 0; |
|
1033 |
vph_p->phys_page[b] = NULL; |
{ |
1034 |
vph_p->refcount --; |
/* Consistency check, for debugging: */ |
1035 |
if (vph_p->refcount < 0) { |
int x1, x1b; // x2, x3; |
1036 |
fatal("alpha_invalidate_tlb_entry(): huh? Problem 2.\n"); |
struct DYNTRANS_L2_64_TABLE *l2; |
1037 |
|
//struct DYNTRANS_L3_64_TABLE *l3; |
1038 |
|
|
1039 |
|
for (x1 = 0; x1 <= mask1; x1 ++) { |
1040 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1041 |
|
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) |
1042 |
|
continue; |
1043 |
|
/* Make sure that this l2 isn't used more than 1 time! */ |
1044 |
|
for (x1b = 0; x1b <= mask1; x1b ++) |
1045 |
|
if (x1 != x1b && |
1046 |
|
l2 == cpu->cd.DYNTRANS_ARCH.l1_64[x1b]) { |
1047 |
|
fatal("L2 reuse: %p\n", l2); |
1048 |
|
exit(1); |
1049 |
|
} |
1050 |
|
} |
1051 |
|
} |
1052 |
|
|
1053 |
|
/* Count how many pages are actually in use: */ |
1054 |
|
{ |
1055 |
|
int n=0, i; |
1056 |
|
for (i=0; i<=mask3; i++) |
1057 |
|
if (l3->vaddr_to_tlbindex[i]) |
1058 |
|
n++; |
1059 |
|
if (n != l3->refcount) { |
1060 |
|
printf("Z: %i in use, but refcount = %i!\n", n, l3->refcount); |
1061 |
|
exit(1); |
1062 |
|
} |
1063 |
|
|
1064 |
|
n = 0; |
1065 |
|
for (i=0; i<=mask3; i++) |
1066 |
|
if (l3->host_load[i] != NULL) |
1067 |
|
n++; |
1068 |
|
if (n != l3->refcount) { |
1069 |
|
printf("ZHL: %i in use, but refcount = %i!\n", n, l3->refcount); |
1070 |
exit(1); |
exit(1); |
1071 |
} |
} |
1072 |
if (vph_p->refcount == 0) { |
} |
1073 |
vph_p->next = cpu->cd.alpha.vph_next_free_page; |
#endif |
1074 |
cpu->cd.alpha.vph_next_free_page = vph_p; |
|
1075 |
if (kernel) |
l3->host_load[x3] = NULL; |
1076 |
cpu->cd.alpha.vph_table0_kernel[a] = |
l3->host_store[x3] = NULL; |
1077 |
cpu->cd.alpha.vph_default_page; |
l3->phys_addr[x3] = 0; |
1078 |
else |
l3->phys_page[x3] = NULL; |
1079 |
cpu->cd.alpha.vph_table0[a] = |
if (l3->vaddr_to_tlbindex[x3] != 0) { |
1080 |
cpu->cd.alpha.vph_default_page; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[ |
1081 |
|
l3->vaddr_to_tlbindex[x3] - 1].valid = 0; |
1082 |
|
l3->refcount --; |
1083 |
|
} |
1084 |
|
l3->vaddr_to_tlbindex[x3] = 0; |
1085 |
|
|
1086 |
|
if (l3->refcount < 0) { |
1087 |
|
fatal("xxx_invalidate_tlb_entry(): huh? Refcount bug.\n"); |
1088 |
|
exit(1); |
1089 |
|
} |
1090 |
|
|
1091 |
|
if (l3->refcount == 0) { |
1092 |
|
l3->next = cpu->cd.DYNTRANS_ARCH.next_free_l3; |
1093 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3; |
1094 |
|
l2->l3[x2] = cpu->cd.DYNTRANS_ARCH.l3_64_dummy; |
1095 |
|
|
1096 |
|
#ifdef BUGHUNT |
1097 |
|
/* Make sure that we're placing a CLEAN page on the |
1098 |
|
freelist: */ |
1099 |
|
{ |
1100 |
|
int i; |
1101 |
|
for (i=0; i<=mask3; i++) |
1102 |
|
if (l3->host_load[i] != NULL) { |
1103 |
|
fatal("TRYING TO RETURN A NON-CLEAN L3 PAGE!\n"); |
1104 |
|
exit(1); |
1105 |
|
} |
1106 |
|
} |
1107 |
|
#endif |
1108 |
|
l2->refcount --; |
1109 |
|
if (l2->refcount < 0) { |
1110 |
|
fatal("xxx_invalidate_tlb_entry(): Refcount bug L2.\n"); |
1111 |
|
exit(1); |
1112 |
|
} |
1113 |
|
if (l2->refcount == 0) { |
1114 |
|
l2->next = cpu->cd.DYNTRANS_ARCH.next_free_l2; |
1115 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2; |
1116 |
|
cpu->cd.DYNTRANS_ARCH.l1_64[x1] = |
1117 |
|
cpu->cd.DYNTRANS_ARCH.l2_64_dummy; |
1118 |
|
} |
1119 |
} |
} |
|
#else /* !DYNTRANS_ALPHA */ |
|
|
#ifdef DYNTRANS_IA64 |
|
|
fatal("IA64: blah blah TODO\n"); |
|
|
#else |
|
|
fatal("Not yet for non-1-level, non-Alpha, non-ia64\n"); |
|
|
#endif /* !DYNTRANS_IA64 */ |
|
|
#endif /* !DYNTRANS_ALPHA */ |
|
1120 |
#endif |
#endif |
1121 |
} |
} |
1122 |
#endif |
#endif |
1132 |
* flags should be one of |
* flags should be one of |
1133 |
* INVALIDATE_PADDR INVALIDATE_VADDR or INVALIDATE_ALL |
* INVALIDATE_PADDR INVALIDATE_VADDR or INVALIDATE_ALL |
1134 |
* |
* |
1135 |
|
* In addition, for INVALIDATE_ALL, INVALIDATE_VADDR_UPPER4 may be set and |
1136 |
|
* bit 31..28 of addr are used to select the virtual addresses to invalidate. |
1137 |
|
* (This is useful for PowerPC emulation, when segment registers are updated.) |
1138 |
|
* |
1139 |
* In the case when all translations are invalidated, paddr doesn't need |
* In the case when all translations are invalidated, paddr doesn't need |
1140 |
* to be supplied. |
* to be supplied. |
1141 |
* |
* |
1143 |
* the quick translation array, not from the linear |
* the quick translation array, not from the linear |
1144 |
* vph_tlb_entry[] array. Hopefully this is enough anyway. |
* vph_tlb_entry[] array. Hopefully this is enough anyway. |
1145 |
*/ |
*/ |
1146 |
void DYNTRANS_INVALIDATE_TC(struct cpu *cpu, uint64_t paddr, int flags) |
void DYNTRANS_INVALIDATE_TC(struct cpu *cpu, uint64_t addr, int flags) |
1147 |
{ |
{ |
1148 |
int r; |
int r; |
1149 |
#ifdef MODE32 |
#ifdef MODE32 |
1151 |
#else |
#else |
1152 |
uint64_t |
uint64_t |
1153 |
#endif |
#endif |
1154 |
addr_page = paddr & ~(DYNTRANS_PAGESIZE - 1); |
addr_page = addr & ~(DYNTRANS_PAGESIZE - 1); |
1155 |
|
|
1156 |
|
/* fatal("invalidate(): "); */ |
1157 |
|
|
1158 |
/* Quick case for virtual addresses: see note above. */ |
/* Quick case for _one_ virtual addresses: see note above. */ |
1159 |
if (flags & INVALIDATE_VADDR) { |
if (flags & INVALIDATE_VADDR) { |
1160 |
|
/* fatal("vaddr 0x%08x\n", (int)addr_page); */ |
1161 |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, addr_page, flags); |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, addr_page, flags); |
1162 |
return; |
return; |
1163 |
} |
} |
1164 |
|
|
1165 |
|
/* Invalidate everything: */ |
1166 |
|
#ifdef DYNTRANS_PPC |
1167 |
|
if (flags & INVALIDATE_ALL && flags & INVALIDATE_VADDR_UPPER4) { |
1168 |
|
/* fatal("all, upper4 (PowerPC segment)\n"); */ |
1169 |
|
for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) { |
1170 |
|
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && |
1171 |
|
(cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page |
1172 |
|
& 0xf0000000) == addr_page) { |
1173 |
|
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd. |
1174 |
|
DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page, |
1175 |
|
0); |
1176 |
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid=0; |
1177 |
|
} |
1178 |
|
} |
1179 |
|
return; |
1180 |
|
} |
1181 |
|
#endif |
1182 |
|
if (flags & INVALIDATE_ALL) { |
1183 |
|
/* fatal("all\n"); */ |
1184 |
|
for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) { |
1185 |
|
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
1186 |
|
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, cpu->cd. |
1187 |
|
DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page, |
1188 |
|
0); |
1189 |
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid=0; |
1190 |
|
} |
1191 |
|
} |
1192 |
|
return; |
1193 |
|
} |
1194 |
|
|
1195 |
|
/* Invalidate a physical page: */ |
1196 |
|
|
1197 |
|
if (!(flags & INVALIDATE_PADDR)) |
1198 |
|
fatal("HUH? Invalidate: Not vaddr, all, or paddr?\n"); |
1199 |
|
|
1200 |
|
/* fatal("addr 0x%08x\n", (int)addr_page); */ |
1201 |
|
|
1202 |
for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) { |
for (r=0; r<DYNTRANS_MAX_VPH_TLB_ENTRIES; r++) { |
1203 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && ( |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && addr_page |
1204 |
(cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page == |
== cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page) { |
|
addr_page && flags & INVALIDATE_PADDR) || |
|
|
flags & INVALIDATE_ALL) ) { |
|
1205 |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, |
1206 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page, |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page, |
1207 |
flags); |
flags); |
1246 |
struct DYNTRANS_TC_PHYSPAGE *ppp, *prev_ppp; |
struct DYNTRANS_TC_PHYSPAGE *ppp, *prev_ppp; |
1247 |
|
|
1248 |
pagenr = DYNTRANS_ADDR_TO_PAGENR(addr); |
pagenr = DYNTRANS_ADDR_TO_PAGENR(addr); |
|
|
|
|
#ifdef MODE32 |
|
|
/* If this page isn't marked as having any translations, |
|
|
then return immediately. */ |
|
|
if (!(cpu->cd.DYNTRANS_ARCH.phystranslation[pagenr >> 5] |
|
|
& 1 << (pagenr & 31))) |
|
|
return; |
|
|
/* Remove the mark: */ |
|
|
cpu->cd.DYNTRANS_ARCH.phystranslation[pagenr >> 5] &= |
|
|
~ (1 << (pagenr & 31)); |
|
|
#endif |
|
|
|
|
1249 |
table_index = PAGENR_TO_TABLE_INDEX(pagenr); |
table_index = PAGENR_TO_TABLE_INDEX(pagenr); |
1250 |
|
|
1251 |
physpage_entryp = &(((uint32_t *)cpu-> |
physpage_entryp = &(((uint32_t *)cpu-> |
1252 |
translation_cache)[table_index]); |
translation_cache)[table_index]); |
1253 |
physpage_ofs = *physpage_entryp; |
physpage_ofs = *physpage_entryp; |
1254 |
|
|
1255 |
|
/* Return immediately if there is no code translation |
1256 |
|
for this page. */ |
1257 |
|
if (physpage_ofs == 0) |
1258 |
|
return; |
1259 |
|
|
1260 |
prev_ppp = ppp = NULL; |
prev_ppp = ppp = NULL; |
1261 |
|
|
1262 |
/* Traverse the physical page chain: */ |
/* Traverse the physical page chain: */ |
1264 |
prev_ppp = ppp; |
prev_ppp = ppp; |
1265 |
ppp = (struct DYNTRANS_TC_PHYSPAGE *) |
ppp = (struct DYNTRANS_TC_PHYSPAGE *) |
1266 |
(cpu->translation_cache + physpage_ofs); |
(cpu->translation_cache + physpage_ofs); |
1267 |
|
|
1268 |
/* If we found the page in the cache, |
/* If we found the page in the cache, |
1269 |
then we're done: */ |
then we're done: */ |
1270 |
if (ppp->physaddr == addr) |
if (ppp->physaddr == addr) |
1271 |
break; |
break; |
1272 |
|
|
1273 |
/* Try the next page in the chain: */ |
/* Try the next page in the chain: */ |
1274 |
physpage_ofs = ppp->next_ofs; |
physpage_ofs = ppp->next_ofs; |
1275 |
} |
} |
1276 |
|
|
1277 |
|
/* If there is no translation, there is no need to go |
1278 |
|
on and try to remove it from the vph_tlb_entry array: */ |
1279 |
if (physpage_ofs == 0) |
if (physpage_ofs == 0) |
1280 |
ppp = NULL; |
return; |
1281 |
|
|
1282 |
#if 1 |
#if 0 |
1283 |
/* |
/* |
1284 |
* "Bypass" the page, removing it from the code cache. |
* "Bypass" the page, removing it from the code cache. |
1285 |
* |
* |
1301 |
* it might be faster since we don't risk wasting cache |
* it might be faster since we don't risk wasting cache |
1302 |
* memory as quickly (which would force unnecessary Restarts). |
* memory as quickly (which would force unnecessary Restarts). |
1303 |
*/ |
*/ |
1304 |
if (ppp != NULL) { |
if (ppp != NULL && ppp->translations != 0) { |
1305 |
/* TODO: Is this faster than copying an entire |
uint32_t x = ppp->translations; /* TODO: |
1306 |
template page? */ |
urk Should be same type as ppp->translations */ |
1307 |
int i; |
int i, j, n, m; |
1308 |
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) |
n = 8 * sizeof(x); |
1309 |
ppp->ics[i].f = |
m = DYNTRANS_IC_ENTRIES_PER_PAGE / n; |
1310 |
|
|
1311 |
|
for (i=0; i<n; i++) { |
1312 |
|
if (x & 1) { |
1313 |
|
for (j=0; j<m; j++) |
1314 |
|
ppp->ics[i*m + j].f = |
1315 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
1316 |
cpu->is_32bit? instr32(to_be_translated) : |
cpu->is_32bit? |
1317 |
|
instr32(to_be_translated) : |
1318 |
#endif |
#endif |
1319 |
instr(to_be_translated); |
instr(to_be_translated); |
1320 |
|
} |
1321 |
|
|
1322 |
|
x >>= 1; |
1323 |
|
} |
1324 |
|
|
1325 |
|
ppp->translations = 0; |
1326 |
} |
} |
1327 |
#endif |
#endif |
1328 |
} |
} |
1329 |
|
|
1330 |
/* Invalidate entries (NOTE: only code entries) in the VPH table: */ |
/* Invalidate entries in the VPH table: */ |
1331 |
for (r = DYNTRANS_MAX_VPH_TLB_ENTRIES/2; |
for (r = 0; r < DYNTRANS_MAX_VPH_TLB_ENTRIES; r ++) { |
|
r < DYNTRANS_MAX_VPH_TLB_ENTRIES; r ++) { |
|
1332 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
1333 |
vaddr_page = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r] |
vaddr_page = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r] |
1334 |
.vaddr_page & ~(DYNTRANS_PAGESIZE-1); |
.vaddr_page & ~(DYNTRANS_PAGESIZE-1); |
1342 |
uint32_t index = |
uint32_t index = |
1343 |
DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
1344 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
|
/* Remove the mark: */ |
|
|
index = DYNTRANS_ADDR_TO_PAGENR(paddr_page); |
|
|
cpu->cd.DYNTRANS_ARCH.phystranslation[ |
|
|
index >> 5] &= ~ (1 << (index & 31)); |
|
1345 |
#else |
#else |
1346 |
/* 2-level: */ |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
1347 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
1348 |
struct alpha_vph_page *vph_p; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
1349 |
uint32_t a, b; |
uint32_t x1, x2, x3; |
1350 |
int kernel = 0; |
struct DYNTRANS_L2_64_TABLE *l2; |
1351 |
|
struct DYNTRANS_L3_64_TABLE *l3; |
1352 |
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) |
|
1353 |
& (ALPHA_LEVEL0 - 1); |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1354 |
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) |
x2 = (vaddr_page >> (64-DYNTRANS_L1N - |
1355 |
& (ALPHA_LEVEL1 - 1); |
DYNTRANS_L2N)) & mask2; |
1356 |
if ((vaddr_page >> ALPHA_TOPSHIFT) == |
x3 = (vaddr_page >> (64-DYNTRANS_L1N - |
1357 |
ALPHA_TOP_KERNEL) { |
DYNTRANS_L2N - DYNTRANS_L3N)) & mask3; |
1358 |
vph_p = cpu->cd.alpha. |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1359 |
vph_table0_kernel[a]; |
l3 = l2->l3[x2]; |
1360 |
kernel = 1; |
l3->phys_page[x3] = NULL; |
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
|
vph_p->phys_page[b] = NULL; |
|
|
#else /* !DYNTRANS_ALPHA */ |
|
|
#ifdef DYNTRANS_IA64 |
|
|
fatal("IA64: blah yo yo TODO\n"); |
|
|
#else |
|
|
fatal("Not yet for non-1-level, non-Alpha, " |
|
|
"non-ia64\n"); |
|
|
#endif /* !DYNTRANS_IA64 */ |
|
|
#endif /* !DYNTRANS_ALPHA */ |
|
1361 |
#endif |
#endif |
1362 |
} |
} |
1363 |
} |
} |
1376 |
void DYNTRANS_UPDATE_TRANSLATION_TABLE(struct cpu *cpu, uint64_t vaddr_page, |
void DYNTRANS_UPDATE_TRANSLATION_TABLE(struct cpu *cpu, uint64_t vaddr_page, |
1377 |
unsigned char *host_page, int writeflag, uint64_t paddr_page) |
unsigned char *host_page, int writeflag, uint64_t paddr_page) |
1378 |
{ |
{ |
1379 |
int64_t lowest, highest = -1; |
int found, r, useraccess = 0; |
|
int found, r, lowest_index, start, end, useraccess = 0; |
|
1380 |
|
|
|
#ifdef DYNTRANS_ALPHA |
|
|
uint32_t a, b; |
|
|
struct alpha_vph_page *vph_p; |
|
|
int kernel = 0; |
|
|
/* fatal("update_translation_table(): v=0x%llx, h=%p w=%i" |
|
|
" p=0x%llx\n", (long long)vaddr_page, host_page, writeflag, |
|
|
(long long)paddr_page); */ |
|
|
#else |
|
1381 |
#ifdef MODE32 |
#ifdef MODE32 |
1382 |
uint32_t index; |
uint32_t index; |
1383 |
vaddr_page &= 0xffffffffULL; |
vaddr_page &= 0xffffffffULL; |
1386 |
" p=0x%x\n", (int)vaddr_page, host_page, writeflag, |
" p=0x%x\n", (int)vaddr_page, host_page, writeflag, |
1387 |
(int)paddr_page); */ |
(int)paddr_page); */ |
1388 |
#else /* !MODE32 */ |
#else /* !MODE32 */ |
1389 |
#ifdef DYNTRANS_IA64 |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
1390 |
fatal("IA64 update todo\n"); |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
1391 |
#else |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
1392 |
fatal("Neither 32-bit, IA64, nor Alpha? 2\n"); |
uint32_t x1, x2, x3; |
1393 |
exit(1); |
struct DYNTRANS_L2_64_TABLE *l2; |
1394 |
#endif |
struct DYNTRANS_L3_64_TABLE *l3; |
1395 |
#endif |
|
1396 |
|
/* fatal("update_translation_table(): v=0x%016"PRIx64", h=%p w=%i" |
1397 |
|
" p=0x%016"PRIx64"\n", (uint64_t)vaddr_page, host_page, writeflag, |
1398 |
|
(uint64_t)paddr_page); */ |
1399 |
#endif |
#endif |
1400 |
|
|
1401 |
|
assert((vaddr_page & (DYNTRANS_PAGESIZE-1)) == 0); |
1402 |
|
assert((paddr_page & (DYNTRANS_PAGESIZE-1)) == 0); |
1403 |
|
|
1404 |
if (writeflag & MEMORY_USER_ACCESS) { |
if (writeflag & MEMORY_USER_ACCESS) { |
1405 |
writeflag &= ~MEMORY_USER_ACCESS; |
writeflag &= ~MEMORY_USER_ACCESS; |
1406 |
useraccess = 1; |
useraccess = 1; |
1407 |
} |
} |
1408 |
|
|
|
start = 0; end = DYNTRANS_MAX_VPH_TLB_ENTRIES / 2; |
|
|
#if 1 |
|
|
/* Half of the TLB used for data, half for code: */ |
|
|
if (writeflag & TLB_CODE) { |
|
|
writeflag &= ~TLB_CODE; |
|
|
start = end; end = DYNTRANS_MAX_VPH_TLB_ENTRIES; |
|
|
} |
|
|
#else |
|
|
/* Data and code entries are mixed. */ |
|
|
end = DYNTRANS_MAX_VPH_TLB_ENTRIES; |
|
|
#endif |
|
|
|
|
1409 |
/* Scan the current TLB entries: */ |
/* Scan the current TLB entries: */ |
|
found = -1; lowest_index = start; |
|
|
lowest = cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[0].timestamp; |
|
1410 |
|
|
1411 |
#ifdef MODE32 |
#ifdef MODE32 |
1412 |
/* NOTE: vaddr_to_tlbindex is one more than the index, so that |
/* |
1413 |
0 becomes -1, which means a miss. */ |
* NOTE 1: vaddr_to_tlbindex is one more than the index, so that |
1414 |
found = cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[ |
* 0 becomes -1, which means a miss. |
1415 |
|
* |
1416 |
|
* NOTE 2: When a miss occurs, instead of scanning the entire tlb |
1417 |
|
* for the entry with the lowest time stamp, just choosing |
1418 |
|
* one at random will work as well. |
1419 |
|
*/ |
1420 |
|
found = (int)cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[ |
1421 |
DYNTRANS_ADDR_TO_PAGENR(vaddr_page)] - 1; |
DYNTRANS_ADDR_TO_PAGENR(vaddr_page)] - 1; |
1422 |
if (found < 0) |
#else |
1423 |
lowest_index = (random() % (end-start)) + start; |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1424 |
if (0) |
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
1425 |
#endif |
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
1426 |
|
& mask3; |
1427 |
for (r=start; r<end; r++) { |
|
1428 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp < lowest) { |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1429 |
lowest = cpu->cd.DYNTRANS_ARCH. |
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) |
1430 |
vph_tlb_entry[r].timestamp; |
found = -1; |
1431 |
lowest_index = r; |
else { |
1432 |
} |
l3 = l2->l3[x2]; |
1433 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp > highest) |
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) |
1434 |
highest = cpu->cd.DYNTRANS_ARCH. |
found = -1; |
1435 |
vph_tlb_entry[r].timestamp; |
else |
1436 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid && |
found = (int)l3->vaddr_to_tlbindex[x3] - 1; |
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page == |
|
|
vaddr_page) { |
|
|
found = r; |
|
|
break; |
|
|
} |
|
1437 |
} |
} |
1438 |
|
#endif |
1439 |
|
|
1440 |
if (found < 0) { |
if (found < 0) { |
1441 |
/* Create the new TLB entry, overwriting the oldest one: */ |
/* Create the new TLB entry, overwriting a "random" entry: */ |
1442 |
r = lowest_index; |
static unsigned int x = 0; |
1443 |
|
r = (x++) % DYNTRANS_MAX_VPH_TLB_ENTRIES; |
1444 |
|
|
1445 |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
if (cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid) { |
1446 |
/* This one has to be invalidated first: */ |
/* This one has to be invalidated first: */ |
1447 |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, |
DYNTRANS_INVALIDATE_TLB_ENTRY(cpu, |
1453 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].host_page = host_page; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].host_page = host_page; |
1454 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page = paddr_page; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].paddr_page = paddr_page; |
1455 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page = vaddr_page; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].vaddr_page = vaddr_page; |
1456 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = writeflag; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = |
1457 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp = highest + 1; |
writeflag & MEM_WRITE; |
1458 |
|
|
1459 |
/* Add the new translation to the table: */ |
/* Add the new translation to the table: */ |
|
#ifdef DYNTRANS_ALPHA |
|
|
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
|
|
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
|
if ((vaddr_page >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
|
|
kernel = 1; |
|
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
|
if (vph_p == cpu->cd.alpha.vph_default_page) { |
|
|
if (cpu->cd.alpha.vph_next_free_page != NULL) { |
|
|
if (kernel) |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel |
|
|
[a] = cpu->cd.alpha. |
|
|
vph_next_free_page; |
|
|
else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a] = |
|
|
cpu->cd.alpha.vph_next_free_page; |
|
|
cpu->cd.alpha.vph_next_free_page = vph_p->next; |
|
|
} else { |
|
|
if (kernel) |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel |
|
|
[a] = malloc(sizeof(struct |
|
|
alpha_vph_page)); |
|
|
else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a] = |
|
|
malloc(sizeof(struct |
|
|
alpha_vph_page)); |
|
|
memset(vph_p, 0, sizeof(struct alpha_vph_page)); |
|
|
} |
|
|
} |
|
|
vph_p->refcount ++; |
|
|
vph_p->host_load[b] = host_page; |
|
|
vph_p->host_store[b] = writeflag? host_page : NULL; |
|
|
vph_p->phys_addr[b] = paddr_page; |
|
|
vph_p->phys_page[b] = NULL; |
|
|
#else |
|
1460 |
#ifdef MODE32 |
#ifdef MODE32 |
1461 |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
1462 |
cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page; |
cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page; |
1467 |
cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = r + 1; |
cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = r + 1; |
1468 |
#ifdef DYNTRANS_ARM |
#ifdef DYNTRANS_ARM |
1469 |
if (useraccess) |
if (useraccess) |
1470 |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 3] |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] |
1471 |
|= 1 << (index & 7); |
|= 1 << (index & 31); |
1472 |
#endif |
#endif |
1473 |
#endif /* 32 */ |
#else /* !MODE32 */ |
1474 |
#endif /* !ALPHA */ |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1475 |
|
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) { |
1476 |
|
if (cpu->cd.DYNTRANS_ARCH.next_free_l2 != NULL) { |
1477 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1] = |
1478 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l2; |
1479 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2->next; |
1480 |
|
} else { |
1481 |
|
int i; |
1482 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1] = |
1483 |
|
malloc(sizeof(struct DYNTRANS_L2_64_TABLE)); |
1484 |
|
l2->refcount = 0; |
1485 |
|
for (i=0; i<(1 << DYNTRANS_L2N); i++) |
1486 |
|
l2->l3[i] = cpu->cd.DYNTRANS_ARCH. |
1487 |
|
l3_64_dummy; |
1488 |
|
} |
1489 |
|
if (l2->refcount != 0) { |
1490 |
|
fatal("Huh? l2 Refcount problem.\n"); |
1491 |
|
exit(1); |
1492 |
|
} |
1493 |
|
} |
1494 |
|
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) { |
1495 |
|
fatal("INTERNAL ERROR L2 reuse\n"); |
1496 |
|
exit(1); |
1497 |
|
} |
1498 |
|
l3 = l2->l3[x2]; |
1499 |
|
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) { |
1500 |
|
if (cpu->cd.DYNTRANS_ARCH.next_free_l3 != NULL) { |
1501 |
|
l3 = l2->l3[x2] = |
1502 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l3; |
1503 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3->next; |
1504 |
|
} else { |
1505 |
|
l3 = l2->l3[x2] = zeroed_alloc(sizeof( |
1506 |
|
struct DYNTRANS_L3_64_TABLE)); |
1507 |
|
} |
1508 |
|
if (l3->refcount != 0) { |
1509 |
|
fatal("Huh? l3 Refcount problem.\n"); |
1510 |
|
exit(1); |
1511 |
|
} |
1512 |
|
l2->refcount ++; |
1513 |
|
} |
1514 |
|
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) { |
1515 |
|
fatal("INTERNAL ERROR L3 reuse\n"); |
1516 |
|
exit(1); |
1517 |
|
} |
1518 |
|
|
1519 |
|
l3->host_load[x3] = host_page; |
1520 |
|
l3->host_store[x3] = writeflag? host_page : NULL; |
1521 |
|
l3->phys_addr[x3] = paddr_page; |
1522 |
|
l3->phys_page[x3] = NULL; |
1523 |
|
l3->vaddr_to_tlbindex[x3] = r + 1; |
1524 |
|
l3->refcount ++; |
1525 |
|
|
1526 |
|
#ifdef BUGHUNT |
1527 |
|
/* Count how many pages are actually in use: */ |
1528 |
|
{ |
1529 |
|
int n=0, i; |
1530 |
|
for (i=0; i<=mask3; i++) |
1531 |
|
if (l3->vaddr_to_tlbindex[i]) |
1532 |
|
n++; |
1533 |
|
if (n != l3->refcount) { |
1534 |
|
printf("X: %i in use, but refcount = %i!\n", n, l3->refcount); |
1535 |
|
exit(1); |
1536 |
|
} |
1537 |
|
|
1538 |
|
n = 0; |
1539 |
|
for (i=0; i<=mask3; i++) |
1540 |
|
if (l3->host_load[i] != NULL) |
1541 |
|
n++; |
1542 |
|
if (n != l3->refcount) { |
1543 |
|
printf("XHL: %i in use, but refcount = %i!\n", n, l3->refcount); |
1544 |
|
exit(1); |
1545 |
|
} |
1546 |
|
} |
1547 |
|
#endif |
1548 |
|
|
1549 |
|
#endif /* !MODE32 */ |
1550 |
} else { |
} else { |
1551 |
/* |
/* |
1552 |
* The translation was already in the TLB. |
* The translation was already in the TLB. |
1553 |
* Writeflag = 0: Do nothing. |
* Writeflag = 0: Do nothing. |
1554 |
* Writeflag = 1: Make sure the page is writable. |
* Writeflag = 1: Make sure the page is writable. |
1555 |
* Writeflag = -1: Downgrade to readonly. |
* Writeflag = MEM_DOWNGRADE: Downgrade to readonly. |
1556 |
*/ |
*/ |
1557 |
r = found; |
r = found; |
1558 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].timestamp = highest + 1; |
if (writeflag & MEM_WRITE) |
|
if (writeflag == 1) |
|
1559 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1; |
1560 |
if (writeflag == -1) |
if (writeflag & MEM_DOWNGRADE) |
1561 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 0; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 0; |
|
#ifdef DYNTRANS_ALPHA |
|
|
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
|
|
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
|
if ((vaddr_page >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
|
|
kernel = 1; |
|
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
|
vph_p->phys_page[b] = NULL; |
|
|
if (vph_p->phys_addr[b] == paddr_page) { |
|
|
if (writeflag == 1) |
|
|
vph_p->host_store[b] = host_page; |
|
|
if (writeflag == -1) |
|
|
vph_p->host_store[b] = NULL; |
|
|
} else { |
|
|
/* Change the entire physical/host mapping: */ |
|
|
vph_p->host_load[b] = host_page; |
|
|
vph_p->host_store[b] = writeflag? host_page : NULL; |
|
|
vph_p->phys_addr[b] = paddr_page; |
|
|
} |
|
|
#else |
|
1562 |
#ifdef MODE32 |
#ifdef MODE32 |
1563 |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
1564 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
1565 |
#ifdef DYNTRANS_ARM |
#ifdef DYNTRANS_ARM |
1566 |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 3]&=~(1<<(index&7)); |
cpu->cd.DYNTRANS_ARCH.is_userpage[index>>5] &= ~(1<<(index&31)); |
1567 |
if (useraccess) |
if (useraccess) |
1568 |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 3] |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] |
1569 |
|= 1 << (index & 7); |
|= 1 << (index & 31); |
1570 |
#endif |
#endif |
1571 |
if (cpu->cd.DYNTRANS_ARCH.phys_addr[index] == paddr_page) { |
if (cpu->cd.DYNTRANS_ARCH.phys_addr[index] == paddr_page) { |
1572 |
if (writeflag == 1) |
if (writeflag & MEM_WRITE) |
1573 |
cpu->cd.DYNTRANS_ARCH.host_store[index] = |
cpu->cd.DYNTRANS_ARCH.host_store[index] = |
1574 |
host_page; |
host_page; |
1575 |
if (writeflag == -1) |
if (writeflag & MEM_DOWNGRADE) |
1576 |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
1577 |
} else { |
} else { |
1578 |
/* Change the entire physical/host mapping: */ |
/* Change the entire physical/host mapping: */ |
1581 |
writeflag? host_page : NULL; |
writeflag? host_page : NULL; |
1582 |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page; |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page; |
1583 |
} |
} |
1584 |
#endif /* 32 */ |
#else /* !MODE32 */ |
1585 |
#endif /* !ALPHA */ |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1586 |
|
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
1587 |
|
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
1588 |
|
& mask3; |
1589 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1590 |
|
l3 = l2->l3[x2]; |
1591 |
|
if (l3->phys_addr[x3] == paddr_page) { |
1592 |
|
if (writeflag & MEM_WRITE) |
1593 |
|
l3->host_store[x3] = host_page; |
1594 |
|
if (writeflag & MEM_DOWNGRADE) |
1595 |
|
l3->host_store[x3] = NULL; |
1596 |
|
} else { |
1597 |
|
/* Change the entire physical/host mapping: */ |
1598 |
|
printf("HOST LOAD 2 set to %p\n", host_page); |
1599 |
|
l3->host_load[x3] = host_page; |
1600 |
|
l3->host_store[x3] = writeflag? host_page : NULL; |
1601 |
|
l3->phys_addr[x3] = paddr_page; |
1602 |
|
} |
1603 |
|
|
1604 |
|
#ifdef BUGHUNT |
1605 |
|
/* Count how many pages are actually in use: */ |
1606 |
|
{ |
1607 |
|
int n=0, i; |
1608 |
|
for (i=0; i<=mask3; i++) |
1609 |
|
if (l3->vaddr_to_tlbindex[i]) |
1610 |
|
n++; |
1611 |
|
if (n != l3->refcount) { |
1612 |
|
printf("Y: %i in use, but refcount = %i!\n", n, l3->refcount); |
1613 |
|
exit(1); |
1614 |
|
} |
1615 |
|
|
1616 |
|
n = 0; |
1617 |
|
for (i=0; i<=mask3; i++) |
1618 |
|
if (l3->host_load[i] != NULL) |
1619 |
|
n++; |
1620 |
|
if (n != l3->refcount) { |
1621 |
|
printf("YHL: %i in use, but refcount = %i!\n", n, l3->refcount); |
1622 |
|
printf("Entry r = %i\n", r); |
1623 |
|
printf("Valid = %i\n", |
1624 |
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].valid); |
1625 |
|
exit(1); |
1626 |
|
} |
1627 |
|
} |
1628 |
|
#endif |
1629 |
|
|
1630 |
|
#endif /* !MODE32 */ |
1631 |
} |
} |
1632 |
} |
} |
1633 |
#endif /* DYNTRANS_UPDATE_TRANSLATION_TABLE */ |
#endif /* DYNTRANS_UPDATE_TRANSLATION_TABLE */ |
1641 |
* Check for breakpoints. |
* Check for breakpoints. |
1642 |
*/ |
*/ |
1643 |
if (!single_step_breakpoint) { |
if (!single_step_breakpoint) { |
1644 |
#ifdef MODE32 |
MODE_uint_t curpc = cpu->pc; |
|
uint32_t curpc = cpu->pc; |
|
|
#else |
|
|
uint64_t curpc = cpu->pc; |
|
|
#endif |
|
1645 |
int i; |
int i; |
1646 |
for (i=0; i<cpu->machine->n_breakpoints; i++) |
for (i=0; i<cpu->machine->n_breakpoints; i++) |
1647 |
if (curpc == |
if (curpc == (MODE_uint_t) |
|
#ifdef MODE32 |
|
|
(uint32_t) |
|
|
#endif |
|
1648 |
cpu->machine->breakpoint_addr[i]) { |
cpu->machine->breakpoint_addr[i]) { |
1649 |
if (!cpu->machine->instruction_trace) { |
if (!cpu->machine->instruction_trace) { |
1650 |
int old_quiet_mode = quiet_mode; |
int old_quiet_mode = quiet_mode; |
1651 |
quiet_mode = 0; |
quiet_mode = 0; |
1652 |
DISASSEMBLE(cpu, ib, 1, 0, 0); |
DISASSEMBLE(cpu, ib, 1, 0); |
1653 |
quiet_mode = old_quiet_mode; |
quiet_mode = old_quiet_mode; |
1654 |
} |
} |
1655 |
fatal("BREAKPOINT: pc = 0x%llx\n(The " |
fatal("BREAKPOINT: pc = 0x%"PRIx64"\n(The " |
1656 |
"instruction has not yet executed.)\n", |
"instruction has not yet executed.)\n", |
1657 |
(long long)cpu->pc); |
(uint64_t)cpu->pc); |
1658 |
|
#ifdef DYNTRANS_DELAYSLOT |
1659 |
|
if (cpu->delay_slot != NOT_DELAYED) |
1660 |
|
fatal("ERROR! Breakpoint in a delay" |
1661 |
|
" slot! Not yet supported.\n"); |
1662 |
|
#endif |
1663 |
single_step_breakpoint = 1; |
single_step_breakpoint = 1; |
1664 |
single_step = 1; |
single_step = ENTER_SINGLE_STEPPING; |
1665 |
goto stop_running_translated; |
goto stop_running_translated; |
1666 |
} |
} |
1667 |
} |
} |
1673 |
|
|
1674 |
#ifdef DYNTRANS_TO_BE_TRANSLATED_TAIL |
#ifdef DYNTRANS_TO_BE_TRANSLATED_TAIL |
1675 |
/* |
/* |
1676 |
* If we end up here, then an instruction was translated. |
* If we end up here, then an instruction was translated. Let's mark |
1677 |
* Mark the page as containing a translation. |
* the page as containing a translation at this part of the page. |
|
* |
|
|
* (Special case for 32-bit mode: set the corresponding bit in the |
|
|
* phystranslation[] array.) |
|
1678 |
*/ |
*/ |
|
#ifdef MODE32 |
|
|
if (!(cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & TRANSLATIONS)) { |
|
|
uint32_t index = DYNTRANS_ADDR_TO_PAGENR(addr); |
|
|
cpu->cd.DYNTRANS_ARCH.phystranslation[index >> 5] |= |
|
|
(1 << (index & 31)); |
|
|
} |
|
|
#endif |
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags |= TRANSLATIONS; |
|
1679 |
|
|
1680 |
|
/* Make sure cur_physpage is in synch: */ |
1681 |
|
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
1682 |
|
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
1683 |
|
|
1684 |
|
{ |
1685 |
|
int x = addr & (DYNTRANS_PAGESIZE - 1); |
1686 |
|
int addr_per_translation_range = DYNTRANS_PAGESIZE / (8 * |
1687 |
|
sizeof(cpu->cd.DYNTRANS_ARCH.cur_physpage->translations)); |
1688 |
|
x /= addr_per_translation_range; |
1689 |
|
|
1690 |
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->translations |= (1 << x); |
1691 |
|
} |
1692 |
|
|
1693 |
/* |
/* |
1694 |
* Now it is time to check for combinations of instructions that can |
* Now it is time to check for combinations of instructions that can |
1695 |
* be converted into a single function call. |
* be converted into a single function call. |
1696 |
* |
* |
1697 |
* Note: Single-stepping or instruction tracing doesn't work with |
* Note: Single-stepping or instruction tracing doesn't work with |
1698 |
* instruction combination. |
* instruction combination. For architectures with delay slots, |
1699 |
|
* we also ignore combinations if the delay slot is across a page |
1700 |
|
* boundary. |
1701 |
*/ |
*/ |
1702 |
if (!single_step && !cpu->machine->instruction_trace) { |
if (!single_step && !cpu->machine->instruction_trace |
1703 |
if (cpu->combination_check != NULL && |
#ifdef DYNTRANS_DELAYSLOT |
1704 |
cpu->machine->speed_tricks) |
&& !in_crosspage_delayslot |
1705 |
cpu->combination_check(cpu, ic, |
#endif |
1706 |
addr & (DYNTRANS_PAGESIZE - 1)); |
&& cpu->cd.DYNTRANS_ARCH.combination_check != NULL |
1707 |
cpu->combination_check = NULL; |
&& cpu->machine->allow_instruction_combinations) { |
1708 |
|
cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic, |
1709 |
|
addr & (DYNTRANS_PAGESIZE - 1)); |
1710 |
|
} |
1711 |
|
|
1712 |
|
cpu->cd.DYNTRANS_ARCH.combination_check = NULL; |
1713 |
|
|
1714 |
|
/* An additional check, to catch some bugs: */ |
1715 |
|
if (ic->f == ( |
1716 |
|
#ifdef DYNTRANS_DUALMODE_32 |
1717 |
|
cpu->is_32bit? instr32(to_be_translated) : |
1718 |
|
#endif |
1719 |
|
instr(to_be_translated))) { |
1720 |
|
fatal("INTERNAL ERROR: ic->f not set!\n"); |
1721 |
|
goto bad; |
1722 |
|
} |
1723 |
|
if (ic->f == NULL) { |
1724 |
|
fatal("INTERNAL ERROR: ic->f == NULL!\n"); |
1725 |
|
goto bad; |
1726 |
} |
} |
1727 |
|
|
1728 |
/* ... and finally execute the translated instruction: */ |
/* ... and finally execute the translated instruction: */ |
1729 |
if (single_step_breakpoint) { |
if ((single_step_breakpoint && cpu->delay_slot == NOT_DELAYED) |
1730 |
|
#ifdef DYNTRANS_DELAYSLOT |
1731 |
|
|| in_crosspage_delayslot |
1732 |
|
#endif |
1733 |
|
) { |
1734 |
/* |
/* |
1735 |
* Special case when single-stepping: Execute the translated |
* Special case when single-stepping: Execute the translated |
1736 |
* instruction, but then replace it with a "to be translated" |
* instruction, but then replace it with a "to be translated" |
1737 |
* directly afterwards. |
* directly afterwards. |
1738 |
*/ |
*/ |
1739 |
single_step_breakpoint = 0; |
single_step_breakpoint = 0; |
1740 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
1741 |
|
cpu->cd.DYNTRANS_ARCH.next_ic = ic + ic->arg[0]; |
1742 |
|
#endif |
1743 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
1744 |
ic->f = |
ic->f = |
1745 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
1746 |
cpu->is_32bit? instr32(to_be_translated) : |
cpu->is_32bit? instr32(to_be_translated) : |
1747 |
#endif |
#endif |
1748 |
instr(to_be_translated); |
instr(to_be_translated); |
1749 |
} else |
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
1750 |
|
ic->arg[0] = 0; |
1751 |
|
#endif |
1752 |
|
} else { |
1753 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
1754 |
|
cpu->cd.DYNTRANS_ARCH.next_ic = ic + ic->arg[0]; |
1755 |
|
|
1756 |
|
/* Additional check, for variable length ISAs: */ |
1757 |
|
if (ic->arg[0] == 0) { |
1758 |
|
fatal("INTERNAL ERROR: instr len = 0!\n"); |
1759 |
|
goto bad; |
1760 |
|
} |
1761 |
|
#endif |
1762 |
|
|
1763 |
|
/* Finally finally :-), execute the instruction: */ |
1764 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
1765 |
|
} |
1766 |
|
|
1767 |
return; |
return; |
1768 |
|
|
1776 |
|
|
1777 |
if (cpu->machine->instruction_trace) |
if (cpu->machine->instruction_trace) |
1778 |
#ifdef MODE32 |
#ifdef MODE32 |
1779 |
fatal(" at 0x%x\n", (int)cpu->pc); |
fatal(" at 0x%"PRIx32"\n", (uint32_t)cpu->pc); |
1780 |
#else |
#else |
1781 |
fatal(" at 0x%llx\n", (long long)cpu->pc); |
fatal(" at 0x%"PRIx64"\n", (uint64_t)cpu->pc); |
1782 |
#endif |
#endif |
1783 |
else { |
else { |
1784 |
fatal(":\n"); |
fatal(":\n"); |
1785 |
DISASSEMBLE(cpu, ib, 1, 0, 0); |
DISASSEMBLE(cpu, ib, 1, 0); |
1786 |
} |
} |
1787 |
|
|
1788 |
cpu->running = 0; |
cpu->running = 0; |
1789 |
cpu->dead = 1; |
|
1790 |
|
/* Note: Single-stepping can jump here. */ |
1791 |
stop_running_translated: |
stop_running_translated: |
1792 |
|
|
1793 |
debugger_n_steps_left_before_interaction = 0; |
debugger_n_steps_left_before_interaction = 0; |
1794 |
cpu->running_translated = 0; |
|
1795 |
ic = cpu->cd.DYNTRANS_ARCH.next_ic = ¬hing_call; |
ic = cpu->cd.DYNTRANS_ARCH.next_ic = ¬hing_call; |
1796 |
cpu->cd.DYNTRANS_ARCH.next_ic ++; |
cpu->cd.DYNTRANS_ARCH.next_ic ++; |
1797 |
|
|
1798 |
/* Execute the "nothing" instruction: */ |
/* Execute the "nothing" instruction: */ |
1799 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
1800 |
|
|
1801 |
#endif /* DYNTRANS_TO_BE_TRANSLATED_TAIL */ |
#endif /* DYNTRANS_TO_BE_TRANSLATED_TAIL */ |
1802 |
|
|