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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.c,v 1.64 2006/09/09 09:04:32 debug Exp $ |
* $Id: cpu_arm.c,v 1.67 2006/12/30 13:30:53 debug Exp $ |
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* |
* |
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* ARM CPU emulation. |
* ARM CPU emulation. |
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* |
* |
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#include "arm_cpu_types.h" |
#include "arm_cpu_types.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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void arm_pc_to_pointers(struct cpu *cpu); |
void arm_pc_to_pointers(struct cpu *cpu); |
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#include "quick_pc_to_pointers.h" |
#include "quick_pc_to_pointers.h" |
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void arm_irq_interrupt_assert(struct interrupt *interrupt); |
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void arm_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* arm_cpu_new(): |
* arm_cpu_new(): |
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for (i=0; i<N_ARM_REGS - 1; i++) |
for (i=0; i<N_ARM_REGS - 1; i++) |
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CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
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/* Register the CPU's "IRQ" and "FIQ" interrupts: */ |
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{ |
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struct interrupt template; |
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char name[50]; |
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snprintf(name, sizeof(name), "%s.irq", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = arm_irq_interrupt_assert; |
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template.interrupt_deassert = arm_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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/* FIQ: TODO */ |
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} |
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return 1; |
return 1; |
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} |
} |
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/* |
/* |
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* arm_cpu_interrupt(): |
* arm_irq_interrupt_assert(): |
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* |
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* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
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* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
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* |
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* TODO: don't hardcode to footbridge! |
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*/ |
*/ |
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int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void arm_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
{ |
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/* fatal("arm_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (irq_nr <= 64) { |
cpu->cd.arm.irq_asserted = 1; |
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if (cpu->machine->md_interrupt != NULL) |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 1); |
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else |
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fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
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" NULL\n", (int)irq_nr); |
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} else { |
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/* Assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 1; |
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} |
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return 1; |
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} |
} |
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/* |
/* |
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* arm_cpu_interrupt_ack(): |
* arm_irq_interrupt_deassert(): |
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*/ |
*/ |
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int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void arm_irq_interrupt_deassert(struct interrupt *interrupt) |
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{ |
{ |
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if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (cpu->machine->md_interrupt != NULL) |
cpu->cd.arm.irq_asserted = 0; |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 0); |
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} else { |
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/* De-assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 0; |
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} |
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return 1; |
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} |
} |
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