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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.c,v 1.60 2006/06/24 21:47:23 debug Exp $ |
* $Id: cpu_arm.c,v 1.67 2006/12/30 13:30:53 debug Exp $ |
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* |
* |
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* ARM CPU emulation. |
* ARM CPU emulation. |
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* |
* |
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#include "arm_cpu_types.h" |
#include "arm_cpu_types.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "of.h" |
#include "of.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#define DYNTRANS_32 |
#define DYNTRANS_32 |
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void arm_pc_to_pointers(struct cpu *cpu); |
void arm_pc_to_pointers(struct cpu *cpu); |
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#include "quick_pc_to_pointers.h" |
#include "quick_pc_to_pointers.h" |
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void arm_irq_interrupt_assert(struct interrupt *interrupt); |
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void arm_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* arm_cpu_new(): |
* arm_cpu_new(): |
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int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
{ |
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int any_cache = 0, i, found; |
int i, found; |
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struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
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/* Scan the list for this cpu type: */ |
/* Scan the list for this cpu type: */ |
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if (found == -1) |
if (found == -1) |
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return 0; |
return 0; |
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cpu->run_instr = arm_run_instr; |
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cpu->memory_rw = arm_memory_rw; |
cpu->memory_rw = arm_memory_rw; |
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cpu->update_translation_table = arm_update_translation_table; |
cpu->update_translation_table = arm_update_translation_table; |
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cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
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cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
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cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
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cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
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/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
if (cpu_id == 0) { |
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debug("%s", cpu->name); |
debug("%s", cpu->name); |
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if (cpu->cd.arm.cpu_type.icache_shift != 0) |
if (cpu->cd.arm.cpu_type.icache_shift != 0 || |
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any_cache = 1; |
cpu->cd.arm.cpu_type.dcache_shift != 0) { |
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if (cpu->cd.arm.cpu_type.dcache_shift != 0) |
int isize = cpu->cd.arm.cpu_type.icache_shift; |
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any_cache = 1; |
int dsize = cpu->cd.arm.cpu_type.dcache_shift; |
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if (any_cache) { |
if (isize != 0) |
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debug(" (I+D = %i+%i KB", |
isize = 1 << (isize - 10); |
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(int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)), |
if (dsize != 0) |
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(int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10))); |
dsize = 1 << (dsize - 10); |
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debug(")"); |
debug(" (I+D = %i+%i KB)", isize, dsize); |
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} |
} |
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} |
} |
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cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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for (i=0; i<N_ARM_REGS - 1; i++) |
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CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
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/* Register the CPU's "IRQ" and "FIQ" interrupts: */ |
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{ |
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struct interrupt template; |
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char name[50]; |
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snprintf(name, sizeof(name), "%s.irq", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = arm_irq_interrupt_assert; |
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template.interrupt_deassert = arm_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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/* FIQ: TODO */ |
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} |
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return 1; |
return 1; |
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} |
} |
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/* |
/* |
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* arm_cpu_register_match(): |
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*/ |
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void arm_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register names: */ |
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for (i=0; i<N_ARM_REGS; i++) { |
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if (strcasecmp(name, arm_regname[i]) == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
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if (i == ARM_PC) |
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m->cpus[cpunr]->pc = *valuep; |
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} else { |
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*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
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if (i == ARM_PC) |
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*valuep = m->cpus[cpunr]->pc; |
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} |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
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* arm_cpu_register_dump(): |
* arm_cpu_register_dump(): |
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* |
* |
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* Dump cpu registers in a relatively readable format. |
* Dump cpu registers in a relatively readable format. |
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/* |
/* |
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* arm_cpu_interrupt(): |
* arm_irq_interrupt_assert(): |
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* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
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* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
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* |
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* TODO: don't hardcode to footbridge! |
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*/ |
*/ |
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int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void arm_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
{ |
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/* fatal("arm_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (irq_nr <= 64) { |
cpu->cd.arm.irq_asserted = 1; |
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if (cpu->machine->md_interrupt != NULL) |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 1); |
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else |
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fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
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" NULL\n", (int)irq_nr); |
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} else { |
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/* Assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 1; |
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} |
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return 1; |
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} |
} |
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/* |
/* |
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* arm_cpu_interrupt_ack(): |
* arm_irq_interrupt_deassert(): |
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*/ |
*/ |
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int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void arm_irq_interrupt_deassert(struct interrupt *interrupt) |
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{ |
{ |
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if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (cpu->machine->md_interrupt != NULL) |
cpu->cd.arm.irq_asserted = 0; |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 0); |
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} else { |
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/* De-assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 0; |
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} |
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return 1; |
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} |
} |
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