25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.61 2006/07/16 13:32:26 debug Exp $ |
* $Id: cpu_arm.c,v 1.64 2006/09/09 09:04:32 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
46 |
#include "memory.h" |
#include "memory.h" |
47 |
#include "misc.h" |
#include "misc.h" |
48 |
#include "of.h" |
#include "of.h" |
49 |
|
#include "settings.h" |
50 |
#include "symbol.h" |
#include "symbol.h" |
51 |
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|
52 |
#define DYNTRANS_32 |
#define DYNTRANS_32 |
78 |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
79 |
struct machine *machine, int cpu_id, char *cpu_type_name) |
struct machine *machine, int cpu_id, char *cpu_type_name) |
80 |
{ |
{ |
81 |
int any_cache = 0, i, found; |
int i, found; |
82 |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
struct arm_cpu_type_def cpu_type_defs[] = ARM_CPU_TYPE_DEFS; |
83 |
|
|
84 |
/* Scan the list for this cpu type: */ |
/* Scan the list for this cpu type: */ |
104 |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
105 |
cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
106 |
cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
107 |
|
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
108 |
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|
109 |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
110 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
122 |
/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
123 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
124 |
debug("%s", cpu->name); |
debug("%s", cpu->name); |
125 |
if (cpu->cd.arm.cpu_type.icache_shift != 0) |
if (cpu->cd.arm.cpu_type.icache_shift != 0 || |
126 |
any_cache = 1; |
cpu->cd.arm.cpu_type.dcache_shift != 0) { |
127 |
if (cpu->cd.arm.cpu_type.dcache_shift != 0) |
int isize = cpu->cd.arm.cpu_type.icache_shift; |
128 |
any_cache = 1; |
int dsize = cpu->cd.arm.cpu_type.dcache_shift; |
129 |
if (any_cache) { |
if (isize != 0) |
130 |
debug(" (I+D = %i+%i KB", |
isize = 1 << (isize - 10); |
131 |
(int)(1 << (cpu->cd.arm.cpu_type.icache_shift-10)), |
if (dsize != 0) |
132 |
(int)(1 << (cpu->cd.arm.cpu_type.dcache_shift-10))); |
dsize = 1 << (dsize - 10); |
133 |
debug(")"); |
debug(" (I+D = %i+%i KB)", isize, dsize); |
134 |
} |
} |
135 |
} |
} |
136 |
|
|
165 |
|
|
166 |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
cpu->cd.arm.flags = cpu->cd.arm.cpsr >> 28; |
167 |
|
|
168 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
169 |
|
for (i=0; i<N_ARM_REGS - 1; i++) |
170 |
|
CPU_SETTINGS_ADD_REGISTER32(arm_regname[i], cpu->cd.arm.r[i]); |
171 |
|
|
172 |
return 1; |
return 1; |
173 |
} |
} |
174 |
|
|
308 |
} |
} |
309 |
} |
} |
310 |
|
|
|
|
|
|
/* |
|
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* arm_cpu_register_match(): |
|
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*/ |
|
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void arm_cpu_register_match(struct machine *m, char *name, |
|
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int writeflag, uint64_t *valuep, int *match_register) |
|
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{ |
|
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int i, cpunr = 0; |
|
|
|
|
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/* CPU number: */ |
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|
|
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/* TODO */ |
|
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|
|
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/* Register names: */ |
|
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for (i=0; i<N_ARM_REGS; i++) { |
|
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if (strcasecmp(name, arm_regname[i]) == 0) { |
|
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if (writeflag) { |
|
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m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
|
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if (i == ARM_PC) |
|
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m->cpus[cpunr]->pc = *valuep; |
|
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} else { |
|
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*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
|
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if (i == ARM_PC) |
|
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*valuep = m->cpus[cpunr]->pc; |
|
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} |
|
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*match_register = 1; |
|
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} |
|
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} |
|
|
} |
|
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|
|
311 |
|
|
312 |
/* |
/* |
313 |
* arm_cpu_register_dump(): |
* arm_cpu_register_dump(): |