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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.c,v 1.44 2005/11/19 18:53:07 debug Exp $ |
* $Id: cpu_arm.c,v 1.54 2006/02/09 20:02:58 debug Exp $ |
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* |
* |
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* ARM CPU emulation. |
* ARM CPU emulation. |
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* |
* |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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|
#include "of.h" |
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#include "symbol.h" |
#include "symbol.h" |
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|
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#define DYNTRANS_32 |
#define DYNTRANS_32 |
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static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
static int arm_exception_to_mode[N_ARM_EXCEPTIONS] = ARM_EXCEPTION_TO_MODE; |
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|
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/* For quick_pc_to_pointers(): */ |
/* For quick_pc_to_pointers(): */ |
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#include "arm_quick_pc_to_pointers.h" |
void arm_pc_to_pointers(struct cpu *cpu); |
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#include "quick_pc_to_pointers.h" |
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/* |
/* |
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cpu->invalidate_code_translation = arm_invalidate_code_translation; |
cpu->invalidate_code_translation = arm_invalidate_code_translation; |
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cpu->translate_address = arm_translate_address; |
cpu->translate_address = arm_translate_address; |
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|
|
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cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
cpu->cd.arm.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.arm.cpu_type.name; |
cpu->name = cpu->cd.arm.cpu_type.name; |
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cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
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|
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cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
cpu->cd.arm.cpsr = ARM_FLAG_I | ARM_FLAG_F; |
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cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
cpu->cd.arm.control = ARM_CONTROL_PROG32 | ARM_CONTROL_DATA32 |
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| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
| ARM_CONTROL_CACHE | ARM_CONTROL_ICACHE | ARM_CONTROL_ALIGN; |
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/* TODO: default auxctrl contents */ |
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|
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if (cpu->machine->prom_emulation) { |
if (cpu->machine->prom_emulation) { |
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cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
cpu->cd.arm.cpsr |= ARM_MODE_SVC32; |
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} |
} |
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} |
} |
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|
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/* TODO: Some of these values (iway and dway) aren't used yet: */ |
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cpu->cd.arm.cachetype = |
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(5 << ARM_CACHETYPE_CLASS_SHIFT) |
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| (1 << ARM_CACHETYPE_HARVARD_SHIFT) |
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| ((cpu->cd.arm.cpu_type.dcache_shift - 9) << |
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ARM_CACHETYPE_DSIZE_SHIFT) |
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| (5 << ARM_CACHETYPE_DASSOC_SHIFT) /* 32-way */ |
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| (2 << ARM_CACHETYPE_DLINE_SHIFT) /* 8 words/line */ |
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| ((cpu->cd.arm.cpu_type.icache_shift - 9) << |
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ARM_CACHETYPE_ISIZE_SHIFT) |
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| (5 << ARM_CACHETYPE_IASSOC_SHIFT) /* 32-way */ |
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| (2 << ARM_CACHETYPE_ILINE_SHIFT); /* 8 words/line */ |
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|
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/* Coprocessor 15 = the system control coprocessor. */ |
/* Coprocessor 15 = the system control coprocessor. */ |
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cpu->cd.arm.coproc[15] = arm_coproc_15; |
cpu->cd.arm.coproc[15] = arm_coproc_15; |
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|
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/* Coprocessor 14 for XScale: */ |
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if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) |
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cpu->cd.arm.coproc[14] = arm_coproc_xscale_14; |
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|
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/* |
/* |
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* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
* NOTE/TODO: Ugly hack for OpenFirmware emulation: |
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*/ |
*/ |
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m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
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if (i == ARM_PC) |
if (i == ARM_PC) |
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m->cpus[cpunr]->pc = *valuep; |
m->cpus[cpunr]->pc = *valuep; |
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} else |
} else { |
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*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
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if (i == ARM_PC) |
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*valuep = m->cpus[cpunr]->pc; |
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} |
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*match_register = 1; |
*match_register = 1; |
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} |
} |
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} |
} |
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} |
} |
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|
|
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if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
if (m != ARM_MODE_USR32 && m != ARM_MODE_SYS32) { |
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debug("cpu%i: usr r8..r14 =", x); |
debug("cpu%i: usr r8-14:", x); |
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for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
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debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.default_r8_r14[i]); |
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debug("\n"); |
debug("\n"); |
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} |
} |
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|
|
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if (m != ARM_MODE_FIQ32) { |
if (m != ARM_MODE_FIQ32) { |
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debug("cpu%i: fiq r8..r14 =", x); |
debug("cpu%i: fiq r8-14:", x); |
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for (i=0; i<7; i++) |
for (i=0; i<7; i++) |
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debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
debug(" %08x", cpu->cd.arm.fiq_r8_r14[i]); |
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debug("\n"); |
debug("\n"); |
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} |
} |
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|
|
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if (m != ARM_MODE_IRQ32) { |
if (m != ARM_MODE_IRQ32) { |
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debug("cpu%i: irq r13..r14 =", x); |
debug("cpu%i: irq r13-14:", x); |
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for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
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debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.irq_r13_r14[i]); |
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debug("\n"); |
debug("\n"); |
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} |
} |
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|
|
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if (m != ARM_MODE_SVC32) { |
if (m != ARM_MODE_SVC32) { |
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debug("cpu%i: svc r13..r14 =", x); |
debug("cpu%i: svc r13-14:", x); |
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for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
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debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.svc_r13_r14[i]); |
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debug("\n"); |
debug("\n"); |
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} |
} |
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|
|
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if (m != ARM_MODE_ABT32) { |
if (m != ARM_MODE_ABT32) { |
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debug("cpu%i: abt r13..r14 =", x); |
debug("cpu%i: abt r13-14:", x); |
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for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
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debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.abt_r13_r14[i]); |
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debug("\n"); |
debug("\n"); |
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} |
} |
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|
|
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if (m != ARM_MODE_UND32) { |
if (m != ARM_MODE_UND32) { |
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debug("cpu%i: und r13..r14 =", x); |
debug("cpu%i: und r13-14:", x); |
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for (i=0; i<2; i++) |
for (i=0; i<2; i++) |
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debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
debug(" %08x", cpu->cd.arm.und_r13_r14[i]); |
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debug("\n"); |
debug("\n"); |
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cpu->cd.arm.control & |
cpu->cd.arm.control & |
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ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
ARM_CONTROL_V? "yes (0xffff0000)" : "no"); |
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|
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/* TODO: auxctrl on which CPU types? */ |
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if (cpu->cd.arm.cpu_type.flags & ARM_XSCALE) { |
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debug("cpu%i: auxctrl = 0x%08x\n", x, |
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cpu->cd.arm.auxctrl); |
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debug("cpu%i: minidata cache attr = 0x%x\n", x, |
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(cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD) |
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>> ARM_AUXCTRL_MD_SHIFT); |
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debug("cpu%i: page table memory attr: %i\n", x, |
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(cpu->cd.arm.auxctrl & ARM_AUXCTRL_P)? 1 : 0); |
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debug("cpu%i: write buffer coalescing: %s\n", x, |
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(cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)? |
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"disabled" : "enabled"); |
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} |
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|
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debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
debug("cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x, |
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cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
cpu->cd.arm.ttb, cpu->cd.arm.dacr); |
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debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
debug("cpu%i: fsr = 0x%08x far = 0x%08x\n", x, |
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"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
"mode 0x%02x (pc=0x%x) ]\n", newmode, (int)cpu->pc); |
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/* exit(1); */ |
/* exit(1); */ |
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} |
} |
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#if 0 |
|
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if (oldmode==0x10 && newmode ==0x17 && cpu->pc == 0x1644f0) |
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single_step = 1; |
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/* 00008554 */ |
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#endif |
|
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cpu->cd.arm.cpsr |= ARM_FLAG_I; |
cpu->cd.arm.cpsr |= ARM_FLAG_I; |
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if (exception_nr == ARM_EXCEPTION_RESET || |
if (exception_nr == ARM_EXCEPTION_RESET || |
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exception_nr == ARM_EXCEPTION_FIQ) |
exception_nr == ARM_EXCEPTION_FIQ) |
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cpu->machine->md_interrupt(cpu->machine, |
cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 1); |
cpu, irq_nr, 1); |
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else |
else |
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fatal("arm_cpu_interrupt(): md_interrupt == NULL\n"); |
fatal("arm_cpu_interrupt(): irq_nr=%i md_interrupt ==" |
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" NULL\n", (int)irq_nr); |
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} else { |
} else { |
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/* Assert ARM IRQs: */ |
/* Assert ARM IRQs: */ |
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cpu->cd.arm.irq_asserted = 1; |
cpu->cd.arm.irq_asserted = 1; |
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* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
* xxxx1100 0100nnnn ddddcccc oooommmm MCRR c,op,Rd,Rn,CRm |
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* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
* xxxx1100 0101nnnn ddddcccc oooommmm MRRC c,op,Rd,Rn,CRm |
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*/ |
*/ |
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if ((iw & 0x0fe00fff) == 0x0c400000) { |
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debug("%s%s\t", iw & 0x100000? "mra" : "mar", |
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condition); |
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if (iw & 0x100000) |
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debug("%s,%s,acc0\n", |
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arm_regname[r12], arm_regname[r16]); |
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else |
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debug("acc0,%s,%s\n", |
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arm_regname[r12], arm_regname[r16]); |
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break; |
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} |
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if ((iw & 0x0fe00000) == 0x0c400000) { |
if ((iw & 0x0fe00000) == 0x0c400000) { |
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debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
debug("%s%s\t", iw & 0x100000? "mrrc" : "mcrr", |
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condition); |
condition); |
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* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
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* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
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*/ |
*/ |
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if ((iw & 0x0ff00ff0) == 0x0e200010) { |
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/* Special case: mia* DSP instructions */ |
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switch ((iw >> 16) & 0xf) { |
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case 0: debug("mia"); break; |
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case 8: debug("miaph"); break; |
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case 12: debug("miaBB"); break; |
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case 13: debug("miaTB"); break; |
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case 14: debug("miaBT"); break; |
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case 15: debug("miaTT"); break; |
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default: debug("UNKNOWN mia vector instruction?"); |
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} |
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debug("%s\t", condition); |
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debug("acc%i,%s,%s\n", ((iw >> 5) & 7), |
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arm_regname[iw & 15], arm_regname[r12]); |
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break; |
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} |
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if (iw & 0x10) { |
if (iw & 0x10) { |
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debug("%s%s\t", |
debug("%s%s\t", |
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(iw & 0x00100000)? "mrc" : "mcr", condition); |
(iw & 0x00100000)? "mrc" : "mcr", condition); |