25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_arm.c,v 1.54 2006/02/09 20:02:58 debug Exp $ |
* $Id: cpu_arm.c,v 1.59 2006/06/16 18:31:25 debug Exp $ |
29 |
* |
* |
30 |
* ARM CPU emulation. |
* ARM CPU emulation. |
31 |
* |
* |
714 |
|
|
715 |
|
|
716 |
/* |
/* |
717 |
|
* arm_cpu_tlbdump(): |
718 |
|
* |
719 |
|
* Called from the debugger to dump the TLB in a readable format. |
720 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
721 |
|
* |
722 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
723 |
|
* just dumped. |
724 |
|
*/ |
725 |
|
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
726 |
|
{ |
727 |
|
} |
728 |
|
|
729 |
|
|
730 |
|
static void add_response_word(struct cpu *cpu, char *r, uint32_t value, |
731 |
|
size_t maxlen) |
732 |
|
{ |
733 |
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
734 |
|
value = ((value & 0xff) << 24) + |
735 |
|
((value & 0xff00) << 8) + |
736 |
|
((value & 0xff0000) >> 8) + |
737 |
|
((value & 0xff000000) >> 24); |
738 |
|
} |
739 |
|
snprintf(r + strlen(r), maxlen - strlen(r), "%08"PRIx32, value); |
740 |
|
} |
741 |
|
|
742 |
|
|
743 |
|
/* |
744 |
|
* arm_cpu_gdb_stub(): |
745 |
|
* |
746 |
|
* Execute a "remote GDB" command. Returns a newly allocated response string |
747 |
|
* on success, NULL on failure. |
748 |
|
*/ |
749 |
|
char *arm_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
750 |
|
{ |
751 |
|
if (strcmp(cmd, "g") == 0) { |
752 |
|
/* 15 gprs, pc, 8 fprs, fps, cpsr. */ |
753 |
|
int i; |
754 |
|
char *r; |
755 |
|
size_t len = 1 + 18 * sizeof(uint32_t); |
756 |
|
r = malloc(len); |
757 |
|
if (r == NULL) { |
758 |
|
fprintf(stderr, "out of memory\n"); |
759 |
|
exit(1); |
760 |
|
} |
761 |
|
r[0] = '\0'; |
762 |
|
for (i=0; i<15; i++) |
763 |
|
add_response_word(cpu, r, cpu->cd.arm.r[i], len); |
764 |
|
add_response_word(cpu, r, cpu->pc, len); |
765 |
|
/* TODO: fprs: */ |
766 |
|
for (i=0; i<8; i++) |
767 |
|
add_response_word(cpu, r, 0, len); |
768 |
|
/* TODO: fps */ |
769 |
|
add_response_word(cpu, r, 0, len); |
770 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
771 |
|
return r; |
772 |
|
} |
773 |
|
|
774 |
|
if (cmd[0] == 'p') { |
775 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
776 |
|
size_t len = 2 * sizeof(uint32_t) + 1; |
777 |
|
char *r = malloc(len); |
778 |
|
r[0] = '\0'; |
779 |
|
if (regnr == ARM_PC) { |
780 |
|
add_response_word(cpu, r, cpu->pc, len); |
781 |
|
} else if (regnr >= 0 && regnr < ARM_PC) { |
782 |
|
add_response_word(cpu, r, cpu->cd.arm.r[regnr], len); |
783 |
|
} else if (regnr >= 0x10 && regnr <= 0x17) { |
784 |
|
/* TODO: fprs */ |
785 |
|
add_response_word(cpu, r, 0, len); |
786 |
|
add_response_word(cpu, r, 0, len); |
787 |
|
add_response_word(cpu, r, 0, len); |
788 |
|
} else if (regnr == 0x18) { |
789 |
|
/* TODO: fps */ |
790 |
|
add_response_word(cpu, r, 0, len); |
791 |
|
} else if (regnr == 0x19) { |
792 |
|
add_response_word(cpu, r, cpu->cd.arm.cpsr, len); |
793 |
|
} |
794 |
|
return r; |
795 |
|
} |
796 |
|
|
797 |
|
fatal("arm_cpu_gdb_stub(): TODO\n"); |
798 |
|
return NULL; |
799 |
|
} |
800 |
|
|
801 |
|
|
802 |
|
/* |
803 |
* arm_cpu_interrupt(): |
* arm_cpu_interrupt(): |
804 |
* |
* |
805 |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
* 0..31 are used as footbridge interrupt numbers, 32..47 = ISA, |
857 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
858 |
*/ |
*/ |
859 |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
860 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
861 |
{ |
{ |
862 |
uint32_t iw, tmp; |
uint32_t iw, tmp; |
863 |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |