25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_alpha_instr.c,v 1.11 2006/06/03 06:46:44 debug Exp $ |
* $Id: cpu_alpha_instr.c,v 1.12 2006/06/30 20:22:53 debug Exp $ |
29 |
* |
* |
30 |
* Alpha instructions. |
* Alpha instructions. |
31 |
* |
* |
879 |
} |
} |
880 |
ic->f = alpha_loadstore[ |
ic->f = alpha_loadstore[ |
881 |
loadstore_type + (imm==0? 4 : 0) + 8 * load |
loadstore_type + (imm==0? 4 : 0) + 8 * load |
882 |
+ (cpu->machine->dyntrans_alignment_check? 16:0) |
+ 16 * llsc]; |
|
+ 32 * llsc]; |
|
883 |
/* Load to the zero register is treated as a prefetch |
/* Load to the zero register is treated as a prefetch |
884 |
hint. It is ignored here. */ |
hint. It is ignored here. */ |
885 |
if (load && ra == ALPHA_ZERO) { |
if (load && ra == ALPHA_ZERO) { |