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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_alpha_instr.c,v 1.3 2005/11/06 22:41:11 debug Exp $ |
* $Id: cpu_alpha_instr.c,v 1.7 2006/02/09 22:40:27 debug Exp $ |
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* |
* |
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* Alpha instructions. |
* Alpha instructions. |
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* |
* |
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*/ |
*/ |
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#include "float_emul.h" |
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/* |
/* |
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* nop: Do nothing. |
* nop: Do nothing. |
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*/ |
*/ |
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/* |
/* |
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* cvttq/c: Convert floating point to quad. |
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* |
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* arg[0] = pointer to rc (destination integer) |
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* arg[2] = pointer to rb (source float) |
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*/ |
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X(cvttq_c) |
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{ |
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struct ieee_float_value fb; |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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reg(ic->arg[0]) = fb.nan? 0 : fb.f; |
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} |
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/* |
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* cvtqt: Convert quad to floating point. |
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* |
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* arg[0] = pointer to rc (destination float) |
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* arg[2] = pointer to rb (source quad integer) |
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*/ |
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X(cvtqt) |
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{ |
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reg(ic->arg[0]) = ieee_store_float_value(reg(ic->arg[2]), |
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IEEE_FMT_D, 0); |
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} |
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/* |
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* fabs, fneg: Floating point absolute value, or negation. |
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* |
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* arg[0] = pointer to rc (destination float) |
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* arg[2] = pointer to rb (source quad integer) |
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*/ |
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X(fabs) |
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{ |
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reg(ic->arg[0]) = reg(ic->arg[2]) & 0x7fffffffffffffffULL; |
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} |
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X(fneg) |
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{ |
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reg(ic->arg[0]) = reg(ic->arg[2]) ^ 0x8000000000000000ULL; |
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} |
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/* |
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* addt, subt, mult, divt: Floating point arithmetic. |
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* |
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* arg[0] = pointer to rc (destination) |
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* arg[1] = pointer to ra (source) |
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* arg[2] = pointer to rb (source) |
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*/ |
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X(addt) |
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{ |
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struct ieee_float_value fa, fb; |
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double res; |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan) |
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res = 0.0; |
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else |
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res = fa.f + fb.f; |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
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IEEE_FMT_D, fa.nan | fb.nan); |
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} |
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X(subt) |
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{ |
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struct ieee_float_value fa, fb; |
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double res; |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan) |
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res = 0.0; |
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else |
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res = fa.f - fb.f; |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
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IEEE_FMT_D, fa.nan | fb.nan); |
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} |
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X(mult) |
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{ |
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struct ieee_float_value fa, fb; |
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double res; |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan) |
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res = 0.0; |
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else |
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res = fa.f * fb.f; |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
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IEEE_FMT_D, fa.nan | fb.nan); |
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} |
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X(divt) |
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{ |
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struct ieee_float_value fa, fb; |
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double res; |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan || fb.f == 0) |
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res = 0.0; |
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else |
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res = fa.f / fb.f; |
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reg(ic->arg[0]) = ieee_store_float_value(res, |
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IEEE_FMT_D, fa.nan | fb.nan || fb.f == 0); |
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} |
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X(cmpteq) |
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{ |
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struct ieee_float_value fa, fb; |
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int res = 0; |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan) |
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res = 0; |
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else |
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res = fa.f == fb.f; |
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reg(ic->arg[0]) = res; |
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} |
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X(cmptlt) |
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{ |
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struct ieee_float_value fa, fb; |
577 |
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int res = 0; |
578 |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan) |
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res = 0; |
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else |
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res = fa.f < fb.f; |
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reg(ic->arg[0]) = res; |
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} |
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X(cmptle) |
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{ |
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struct ieee_float_value fa, fb; |
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int res = 0; |
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ieee_interpret_float_value(reg(ic->arg[1]), &fa, IEEE_FMT_D); |
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ieee_interpret_float_value(reg(ic->arg[2]), &fb, IEEE_FMT_D); |
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if (fa.nan | fb.nan) |
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res = 0; |
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else |
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res = fa.f <= fb.f; |
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reg(ic->arg[0]) = res; |
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} |
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/* |
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* mull: Signed Multiply 32x32 => 32. |
* mull: Signed Multiply 32x32 => 32. |
602 |
* |
* |
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* arg[0] = pointer to destination uint64_t |
* arg[0] = pointer to destination uint64_t |
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unsigned char ib[4]; |
unsigned char ib[4]; |
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void (*samepage_function)(struct cpu *, struct alpha_instr_call *); |
void (*samepage_function)(struct cpu *, struct alpha_instr_call *); |
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int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc; |
int opcode, ra, rb, func, rc, imm, load, loadstore_type, fp, llsc; |
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#ifdef DYNTRANS_BACKEND |
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int simple = 0; |
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#endif |
760 |
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/* Figure out the (virtual) address of the instruction: */ |
/* Figure out the (virtual) address of the instruction: */ |
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low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page) |
low_pc = ((size_t)ic - (size_t)cpu->cd.alpha.cur_ic_page) |
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ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra]; |
ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra]; |
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ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
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switch (func & 0x7ff) { |
switch (func & 0x7ff) { |
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case 0x02f: ic->f = instr(cvttq_c); break; |
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case 0x0a0: ic->f = instr(addt); break; |
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case 0x0a1: ic->f = instr(subt); break; |
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case 0x0a2: ic->f = instr(mult); break; |
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case 0x0a3: ic->f = instr(divt); break; |
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case 0x0a5: ic->f = instr(cmpteq); break; |
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case 0x0a6: ic->f = instr(cmptlt); break; |
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case 0x0a7: ic->f = instr(cmptle); break; |
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case 0x0be: ic->f = instr(cvtqt); break; |
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default:fatal("[ Alpha: unimplemented function 0x%03x for" |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
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" opcode 0x%02x ]\n", func, opcode); |
" opcode 0x%02x ]\n", func, opcode); |
1117 |
goto bad; |
goto bad; |
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ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
ic->arg[2] = (size_t) &cpu->cd.alpha.f[rb]; |
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switch (func & 0x7ff) { |
switch (func & 0x7ff) { |
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case 0x020: |
case 0x020: |
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/* fclr: */ |
/* fabs (or fclr): */ |
1131 |
if (ra == 31 && rb == 31) |
if (ra == 31 && rb == 31) |
1132 |
ic->f = instr(clear); |
ic->f = instr(clear); |
1133 |
else { |
else |
1134 |
/* fabs: */ |
ic->f = instr(fabs); |
1135 |
goto bad; |
break; |
1136 |
} |
case 0x021: |
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ic->f = instr(fneg); |
1138 |
break; |
break; |
1139 |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
default:fatal("[ Alpha: unimplemented function 0x%03x for" |
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" opcode 0x%02x ]\n", func, opcode); |
" opcode 0x%02x ]\n", func, opcode); |
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goto bad; |
goto bad; |
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} |
} |
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break; |
break; |
1188 |
case 0x30: /* BR */ |
case 0x30: /* BR */ |
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case 0x34: /* BSR */ |
case 0x31: /* FBEQ */ |
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case 0x34: /* BSR */ |
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case 0x35: /* FBNE */ |
1192 |
case 0x38: /* BLBC */ |
case 0x38: /* BLBC */ |
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case 0x39: /* BEQ */ |
case 0x39: /* BEQ */ |
1194 |
case 0x3a: /* BLT */ |
case 0x3a: /* BLT */ |
1195 |
case 0x3b: /* BLE */ |
case 0x3b: /* BLE */ |
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case 0x3c: /* BLBS */ |
case 0x3c: /* BLBS */ |
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case 0x3d: /* BNE */ |
case 0x3d: /* BNE */ |
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case 0x3e: /* BGE */ |
case 0x3e: /* BGE */ |
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case 0x3f: /* BGT */ |
case 0x3f: /* BGT */ |
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/* To avoid a GCC warning: */ |
/* To avoid a GCC warning: */ |
1201 |
samepage_function = instr(nop); |
samepage_function = instr(nop); |
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fp = 0; |
1203 |
switch (opcode) { |
switch (opcode) { |
1204 |
case 0x30: |
case 0x30: |
1205 |
case 0x34: |
case 0x34: |
1214 |
ic->f = instr(blbc); |
ic->f = instr(blbc); |
1215 |
samepage_function = instr(blbc_samepage); |
samepage_function = instr(blbc_samepage); |
1216 |
break; |
break; |
1217 |
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case 0x31: |
1218 |
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fp = 1; |
1219 |
case 0x39: |
case 0x39: |
1220 |
ic->f = instr(beq); |
ic->f = instr(beq); |
1221 |
samepage_function = instr(beq_samepage); |
samepage_function = instr(beq_samepage); |
1232 |
ic->f = instr(blbs); |
ic->f = instr(blbs); |
1233 |
samepage_function = instr(blbs_samepage); |
samepage_function = instr(blbs_samepage); |
1234 |
break; |
break; |
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case 0x35: |
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fp = 1; |
1237 |
case 0x3d: |
case 0x3d: |
1238 |
ic->f = instr(bne); |
ic->f = instr(bne); |
1239 |
samepage_function = instr(bne_samepage); |
samepage_function = instr(bne_samepage); |
1247 |
samepage_function = instr(bgt_samepage); |
samepage_function = instr(bgt_samepage); |
1248 |
break; |
break; |
1249 |
} |
} |
1250 |
ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra]; |
if (fp) |
1251 |
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ic->arg[1] = (size_t) &cpu->cd.alpha.f[ra]; |
1252 |
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else |
1253 |
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ic->arg[1] = (size_t) &cpu->cd.alpha.r[ra]; |
1254 |
ic->arg[0] = (iword & 0x001fffff) << 2; |
ic->arg[0] = (iword & 0x001fffff) << 2; |
1255 |
/* Sign-extend: */ |
/* Sign-extend: */ |
1256 |
if (ic->arg[0] & 0x00400000) |
if (ic->arg[0] & 0x00400000) |