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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_alpha.c,v 1.19 2006/07/20 21:52:59 debug Exp $ |
* $Id: cpu_alpha.c,v 1.27 2007/06/07 15:36:24 debug Exp $ |
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* |
* |
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* Alpha CPU emulation. |
* Alpha CPU emulation. |
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* |
* |
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#include <ctype.h> |
#include <ctype.h> |
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#include "cpu.h" |
#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#include "timer.h" |
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#define DYNTRANS_8K |
#define DYNTRANS_8K |
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#define DYNTRANS_PAGESIZE 8192 |
#define DYNTRANS_PAGESIZE 8192 |
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#include "tmp_alpha_head.c" |
#include "tmp_alpha_head.c" |
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extern int native_code_translation_enabled; |
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/* Alpha symbolic register names: */ |
/* Alpha symbolic register names: */ |
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static char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; |
static char *alpha_regname[N_ALPHA_REGS] = ALPHA_REG_NAMES; |
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void alpha_irq_interrupt_assert(struct interrupt *interrupt); |
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void alpha_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* alpha_cpu_new(): |
* alpha_cpu_new(): |
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if (cpu_type_defs[i].name == NULL) |
if (cpu_type_defs[i].name == NULL) |
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return 0; |
return 0; |
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cpu->is_32bit = 0; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->memory_rw = alpha_memory_rw; |
cpu->memory_rw = alpha_memory_rw; |
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cpu->run_instr = alpha_run_instr; |
cpu->run_instr = alpha_run_instr; |
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cpu->translate_v2p = alpha_translate_v2p; |
cpu->translate_v2p = alpha_translate_v2p; |
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cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
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alpha_invalidate_translation_caches; |
alpha_invalidate_translation_caches; |
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cpu->invalidate_code_translation = alpha_invalidate_code_translation; |
cpu->invalidate_code_translation = alpha_invalidate_code_translation; |
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cpu->is_32bit = 0; |
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cpu->cd.alpha.cpu_type = cpu_type_defs[i]; |
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/* Only show name and caches etc for CPU nr 0: */ |
/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
if (cpu_id == 0) { |
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cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL; |
cpu->cd.alpha.r[ALPHA_SP] = 0xfffffc000000ff00ULL; |
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/* Set up dummy kentry pointers to something which crashes |
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the machine: */ |
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store_32bit_word(cpu, 0x10010, 0x3fffffc); |
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for (i=0; i<N_ALPHA_KENTRY; i++) |
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cpu->cd.alpha.kentry[i] = 0x10010; |
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/* Bogus initial context (will be overwritten on first |
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context switch): */ |
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cpu->cd.alpha.ctx = 0x10100; |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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for (i=0; i<N_ALPHA_REGS; i++) |
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CPU_SETTINGS_ADD_REGISTER64(alpha_regname[i], |
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cpu->cd.alpha.r[i]); |
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/* Register the CPU interrupt pin: */ |
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{ |
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struct interrupt template; |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = cpu->path; |
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template.extra = cpu; |
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template.interrupt_assert = alpha_irq_interrupt_assert; |
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template.interrupt_deassert = alpha_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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if (native_code_translation_enabled) |
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cpu->sampling_timer = timer_add(CPU_SAMPLE_TIMER_HZ, |
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alpha_timer_sample_tick, cpu); |
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return 1; |
return 1; |
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} |
} |
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/* |
/* |
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* alpha_cpu_register_match(): |
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*/ |
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void alpha_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} |
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/* Register names: */ |
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for (i=0; i<N_ALPHA_REGS; i++) { |
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if (strcasecmp(name, alpha_regname[i]) == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.alpha.r[i] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.alpha.r[i]; |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
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* alpha_cpu_register_dump(): |
* alpha_cpu_register_dump(): |
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* |
* |
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* Dump cpu registers in a relatively readable format. |
* Dump cpu registers in a relatively readable format. |
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} |
} |
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static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
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size_t maxlen, int len) |
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{ |
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char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
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if (len == 4) |
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value &= 0xffffffffULL; |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
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if (len == 4) { |
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value = ((value & 0xff) << 24) + |
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((value & 0xff00) << 8) + |
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((value & 0xff0000) >> 8) + |
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((value & 0xff000000) >> 24); |
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} else { |
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value = ((value & 0xff) << 56) + |
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((value & 0xff00) << 40) + |
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((value & 0xff0000) << 24) + |
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((value & 0xff000000ULL) << 8) + |
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((value & 0xff00000000ULL) >> 8) + |
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((value & 0xff0000000000ULL) >> 24) + |
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((value & 0xff000000000000ULL) >> 40) + |
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((value & 0xff00000000000000ULL) >> 56); |
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} |
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} |
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snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
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} |
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/* |
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* alpha_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *alpha_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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if (strcmp(cmd, "g") == 0) { |
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int i; |
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char *r; |
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size_t wlen = cpu->is_32bit? |
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sizeof(uint32_t) : sizeof(uint64_t); |
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size_t len = 1 + 76 * wlen; |
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r = malloc(len); |
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if (r == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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r[0] = '\0'; |
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for (i=0; i<128; i++) |
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add_response_word(cpu, r, i, len, wlen); |
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return r; |
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} |
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if (cmd[0] == 'p') { |
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int regnr = strtol(cmd + 1, NULL, 16); |
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size_t wlen = cpu->is_32bit? |
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sizeof(uint32_t) : sizeof(uint64_t); |
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size_t len = 2 * wlen + 1; |
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char *r = malloc(len); |
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r[0] = '\0'; |
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if (regnr >= 0 && regnr <= 31) { |
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add_response_word(cpu, r, |
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cpu->cd.alpha.r[regnr], len, wlen); |
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} else if (regnr >= 32 && regnr <= 62) { |
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add_response_word(cpu, r, |
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cpu->cd.alpha.f[regnr - 32], len, wlen); |
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} else if (regnr == 0x3f) { |
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add_response_word(cpu, r, cpu->cd.alpha.fpcr, |
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len, wlen); |
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} else if (regnr == 0x40) { |
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add_response_word(cpu, r, cpu->pc, len, wlen); |
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} else { |
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/* Unimplemented: */ |
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add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
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} |
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return r; |
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} |
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fatal("alpha_cpu_gdb_stub(): TODO\n"); |
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return NULL; |
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} |
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/* |
/* |
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* alpha_cpu_interrupt(): |
* alpha_irq_interrupt_assert(): |
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* alpha_irq_interrupt_deassert(): |
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*/ |
*/ |
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int alpha_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void alpha_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
{ |
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fatal("alpha_cpu_interrupt(): TODO\n"); |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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return 0; |
cpu->cd.alpha.irq_asserted = 1; |
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} |
} |
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void alpha_irq_interrupt_deassert(struct interrupt *interrupt) |
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/* |
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* alpha_cpu_interrupt_ack(): |
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*/ |
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int alpha_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
{ |
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/* fatal("alpha_cpu_interrupt_ack(): TODO\n"); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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return 0; |
cpu->cd.alpha.irq_asserted = 0; |
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} |
} |
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case 0x061: mnem = "amask"; break; |
case 0x061: mnem = "amask"; break; |
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case 0x064: mnem = "cmovle"; break; |
case 0x064: mnem = "cmovle"; break; |
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case 0x066: mnem = "cmovgt"; break; |
case 0x066: mnem = "cmovgt"; break; |
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case 0x06c: mnem = "implver"; break; |
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default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
default:debug("UNIMPLEMENTED opcode 0x%x func 0x%x\n", |
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opcode, func); |
opcode, func); |
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} |
} |
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else |
else |
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debug("mov\t%s,%s\n", alpha_regname[ra], |
debug("mov\t%s,%s\n", alpha_regname[ra], |
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alpha_regname[rc]); |
alpha_regname[rc]); |
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} else if (func == 0x1ec) { |
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/* implver */ |
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debug("%s\t%s\n", mnem, alpha_regname[rc]); |
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} else if (func & 0x80) |
} else if (func & 0x80) |
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debug("%s\t%s,0x%x,%s\n", mnem, |
debug("%s\t%s,0x%x,%s\n", mnem, |
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alpha_regname[ra], (rb << 3) + (func >> 8), |
alpha_regname[ra], (rb << 3) + (func >> 8), |