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$Id: README_DYNTRANS,v 1.12 2006/10/13 05:01:19 debug Exp $ |
$Id: README_DYNTRANS,v 1.13 2007/02/11 10:47:30 debug Exp $ |
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This README is old. Hm. |
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Dyntrans TODO: |
Dyntrans TODO: |
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(*) Delay slot in SHcompact? |
(*) Delay slot in SHcompact? |
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x) instr_call sequence analysis support? (For handtuning combinations.) |
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x) opcode statistics support? |
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TODO: is instr_call statistics enough? |
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x) load/stores: |
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o) perhaps refactor/reuse common load/store code? |
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o) support for archs that allow transparent |
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unaligned load/stores (ppc, x86 etc) |
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o) alignment checks ==> exceptions |
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o) native byte order ==> faster loads, etc. |
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x) actual cache emulation |
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x) SMP: detect when an instruction such as ll/sc or cas is used, |
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and "synchronize" approximately the number of executed instructions |
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(or cycles) across all CPUs. |
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Problem: devices such as dev_mp don't work well with such a synch. |
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scheme. |
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x) support for variable-length instructions (x86, m68k, i960, ...) |
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Current solution: ic->arg[0] contains the length of the |
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instruction (in bytes), and next_ic is |
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automatically updated. |
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Problem: what about instructions crossing a (virtual) |
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page boundary? They cannot be translated once |
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and for all :( and must be interpreted slowly! |
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x) support for THUMB, MIPS16, userland SH (arm, mips, sh) |
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x) support for Delay slots! (mips, sparc, hppa, SHcompact?) |
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x) various register-window archs (SPARC etc) |
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x) Alpha: hahaha, zapnot and inserts/extracts don't |
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compile into very nice code :-| fix this |
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Solution: if short assembly language snippets can be |
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compiled on the current host, then compile such snippets |
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for alpha_instr_zapnot etc. |
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x) pc532? 6502? 6800? etc |
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